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  • Intel® MAX 10 Commercial [10M08SAU169C8G]

    • Package: UBGA-169

    • Speed Grade: C8 (Slowest)

    • Temperature: 0°C to 85°C

    • Package compatible device 10M08...10M16 as assembly variant on request possible

  • SDRAM Memory up to 32 Mbyte (8Mbyte default)

  • USB 2.0 Multipurpose UART/FIFO IC (FT2232H)

    • 4 Kbit EEPROM Memory for FTDI configuration data
    • Micro USB Receptacle (communication and power)
  • SPI Flash - NOT INSTALLED (only special option)

  • 8x User LED 
  • Micro USB2 Receptacle 90USB Connector

  • 16 Bit Analog to Digital Converter with 1 MSPS or 500 kSPS

  • 2x SMA Female Connector

  • I/O interface: 23x GPIO

  • Power Supply: 5V (from USB)

  • Dimension: 25 mm x 86.5 mm

  • Others:

    • Instrumentation Amplifier

    • Differential Amplifier

    • Operational Amplifier

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  1. SMA Connector, J5...6
  2. Amplifier, U12
  3. Analog to Digital Converter, U6
  4. Voltage Reference, U8
  5. Voltage Regulator, U10 - U13 - U16
  6. Switching Voltage Regulator/LDO, U11 - U4
  7. SDRAM Memory, U2
  8. Intel® MAX 10 FPGA, U1
  9. SPI Flash Memory, U5 (not populated)
  10. 12.00 MHz MEMS oscillator, U7
  11. FTDI USB2 USB to JTAG/UART/FIFO, U3
  12. User LEDs, D2...9
  13. 4Kb EEPROM, U9
  14. Configuration LED (Red) , D10
  15. Power-on LED (Green), D1
  16. Push button, S1...2
  17. Micro USB Connector, J9
  18. 1x14 pin header, J2 (Not assembled)
  19. 1x6 pin header, J4 (Not assembled)
  20. Jumper, J3
  21. 1x14 pin header, J1 (Not assembled)

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  • Overview of Boot Mode, Reset, Enables.

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.

FPGA Reconfigration can be triggered by pressing push button S1.

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Signal

Push ButtonPin HeaderNote

RESET

S1J2Connected to nCONFIG


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Clock SourceSchematic NameFrequencyNote
Microchip MEMS Oscillator, U7CLK12M12.00 MHz

Connected to FTDI FT2232 U3, pin 3.

Connected to FPGA bank 2, pin H6.


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DateRevisionContributorDescription

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  • update notes for variants
  • major cleanup multiply sections

2019-09-20

v.56Kilian Jahn
  • update notes for variants
2019-06-05v.55ED
  • Technical Specifications updated

  • Power Rails updated

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