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On-board Peripherals

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Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

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hidden true id Comments
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchor	Table_OBP
title	On board peripherals

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SDRAM

TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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anchor	Table_OBP_SDRAM
title	SDRAM interface IOs and pins

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Signal Schematic Name

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A0 ... A13

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BA0 / BA1

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bank 3

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DQ0 ... DQ15

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bank 6

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DQM0 ... DQM1

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bank 6

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CS

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bank 3

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CKE

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bank 3

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RAS

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bank 3

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Row Address Strobe

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CAS

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bank 3

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Column Address Strobe

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FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

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anchor	Table_OBP_FTDI
title	FTDI chip interfaces and pins

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FPGA bank 1B, pin G1

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SPI Flash Memory

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

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anchor	Table_OBP_QSPI
title	Quad SPI Flash memory interface

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FPGA bank 8, pin C4

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VBUS USB_VBUS D+ FTDI U3, DP pin D- FTDI U3, DM pin

JTAG Interface

JTAG access to the TEI0016 SoM through pin header connector J4.

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anchor Table_SIP_JTG title JTAG pins connection
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true JTAG Signal Pin Header Connector Note TMS J4-6 TDI J4-5 TDO J4-4 TCK J4-3 JTAG_EN J4-2 Pulled-up to 3.3V.

On-board Peripherals

Page properties
hidden true id Comments
Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

Page properties
hidden true id Comments
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Scroll Title
anchor Table_OBP title On board peripherals
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Chip/Interface Designator Notes 77530151 U2 FTDI FT2232H U3 JTAG/UART/FIFO 77530151 U5 77530151 U9 Oscillator U7 12 MHz clock source 77530151 U6 Analog to Digital Converter 8x User LEDs D2...9 Red LEDs Push Buttons S1...2

SDRAM

TEI0016 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface.

Page properties
hidden true id Comments
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

Scroll Title
anchor Table_OBP_SDRAM title SDRAM interface IOs and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true SDRAM I/O Signals Signal Schematic Name Connected to Notes Address inputs A0 ... A13 bank 3 - Bank address inputs BA0 / BA1 bank 3 - Data input/output DQ0 ... DQ15 bank 6 - Data mask DQM0 ... DQM1 bank 6 - Clock CLK bank 3 - Control Signals CS bank 3 Chip select CKE bank 3 Clock enable RAS bank 3 Row Address Strobe CAS bank 3 Column Address Strobe WE bank 3 Write Enable

FTDI FT2232H

The FTDI chip U3 converts signals from USB to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the features of the FT2232H chip. FTDI FT2232H chip channel A is used in MPPSE mode for JTAG. Channel B is configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

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anchor Table_OBP_FTDI title FTDI chip interfaces and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true FTDI Chip U3 Pin Signal Schematic Name Connected to Notes ADBUS0 TCK FPGA bank 1B, pin G2 JTAG interface ADBUS1 TDI FPGA bank 1B, pin F5 ADBUS2 TDO FPGA bank 1B, pin F6 ADBUS3 TMS FPGA bank 1B, pin G1 BDBUS0 BDBUS0 FPGA bank 8, pin A4 User configurable BDBUS1 BDBUS1 FPGA bank 8, pin B4 User configurable BDBUS2 BDBUS2 FPGA bank 8, pin B5 User configurable BDBUS3 BDBUS3 FPGA bank 8, pin A6 User configurable BDBUS4 BDBUS4 FPGA bank 8, pin B6 User configurable BDBUS5 BDBUS5 FPGA bank 8, pin A7 User configurable BDBUS6 BDBUS6 FPGA bank 6, pin C11 BDBUS7 BDBUS7 FPGA bank 3, pin J7 BCBUS0 BCBUS0 FPGA bank 5, pin J9 BCBUS1 BCBUS1 FPGA bank 3, pin K5 BCBUS2 BCBUS2 FPGA bank 3, pin K5 BCBUS3 BCBUS3 FPGA bank 3, pin K5 BCBUS4 BCBUS4 FPGA bank 3, pin K5

SPI Flash

Optional SPI flash device maybe assembled in custom variants, normally it is not populated

EEPROM

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

Scroll Title
anchor Table_OBP_EEPQSPI title I2C EEPROM interface MIOs and pinsQuad SPI Flash memory interface
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Signal Schematic Name Connected to Notes EECS FTDI U3, Pin EECS EECLK FTDI U3, Pin EECLK EEDATA FTDI U3, Pin EEDATA

A2D Convertor

F_CS FPGA bank 8, pin B3 Chip select F_CLK FPGA bank 8, pin A3 Clock F_DI FPGA bank 8, pin A2 Data in / out nSTATUS FPGA bank 8, pin C4 Data in / out, configuration dual-purpose pin of FPGA DEVCLRN FPGA bank 8, pin B9 Data in / out, configuration dual-purpose pin of FPGA F_DO FPGA bank 8, pin B2 Data in / out

EEPROM

The configuration of FTDI FT2232H chip is pre-programmed in the EEPROM U9The TEI0010 board is equipped with the Analog Devices AD4003BCPZ, 18-bit A2D converter (ADC).

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anchor Table_OBP_A2DEEP title A2D converter I2C EEPROM interface MIOs and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true PinsSchematic Connected to Notes IN+ Diff Amplifier U14, VOUT- IN- Diff Amplifier U14, VOUT+ SDI Bank 2, ADC_SDI SDO Bank 2, ADC_SDO SCK Bank 2, ADC_SCK CNV Bank 2, ADC_CNV

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EECS FTDI U3, Pin EECS EECLK FTDI U3, Pin EECLK EEDATA FTDI U3, Pin EEDATA

ADC

The boards with article nuber - TEI0016-03-08-C8A - are equipped with the Analog DevicesADC - ADAQ7988BCCZ - 16-bit 500kSPS,
boards wit article number TEI0016-03-08-C8B are equipped with the Analog Devices ADC - ADAQ7980BCCZ - 16-bit 1MSPS.

The ADC can be distinguished via its part code:

• TEI0016-03-08-C8A: ADAQ7988BCCZ - 16-bit 500kSPS - starts with Y6H
• TEI0016-03-08-C8B: ADAQ7980BCCZ - 16-bit 1.0MSPS - starts with Y6F

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anchor TableFigure_OBPOV_LEDBD title On-board LEDsTEI0016 part code variants
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Designator	Color	Connected to	Active Level	Note
D2...9	Red	LED1...8	Active High	User LEDs
D10	Red	CONF_DONE	Active Low	Configuration DONE LED
D1	Green	3.3V Power Rail	Active High	After power on it will be on

Micro-USB2 Connector

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anchor Table_OBP_USBADC title Micro USB-2 connector ADC converter interface and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Pins Connected to	Note
VBUS	USB_VBUS	It is connected to GND
D+	FTDI U3, DP pin	D-	FTDI U3, DM pin

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Notes IN+ U8, VOUT IN- U12, VOUT SDI Bank 2, ADC_SDI SDO Bank 2, ADC_SDO SCK Bank 2, ADC_SCK CNV Bank 2, ADC_CNV

LEDs

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anchor Table_OBP_CLKLED title On-board LEDs Osillators
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Clock Source	Schematic Name	Frequency	Note
Microchip MEMS Oscillator, U7	CLK12M	12.00 MHz	Connected to FTDI FT2232 U3, pin 3 Connected to FPGA SoC bank 2, pin H6

Power and Power-On Sequence

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hidden	true
id	Comments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

• Power on-sequence
• Power distribution
• Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Designator Color Connected to Active Level Note D2...9 Red LED1...8 Active High User LEDs D10 Red CONF_DONE Active Low Configuration DONE LED D1 Green 3.3V Power Rail Active High After power on it will be on.

Push Buttons

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anchor Table_OBP_LED title On-board Push Buttons
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Designator Connected to Functionality Note S1 RESET General reset S2 USER_BTN User push button Connected to FPGA Bank 8.

Clock Sources

Power Supply

To power-up the module, power supply with minimum current capability of 1A is recommended.

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Scroll Title
anchor Table_PWROBP_PCCLK title Power ConsumptionOsillators
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true
Power Input Pin	Typical Current
VIN	TBD*

* TBD - To Be Determined

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sortEnabled false cellHighlighting true Clock Source Schematic Name Frequency Note MEMS Oscillator, U7 CLK12M 12.00 MHz Connected to FTDI FT2232 U3, pin 3. Connected to FPGA bank 2, pin H6.

Power and Power-On Sequence

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hidden true id Comments
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: Power on-sequence Power distribution Voltage monitoring circuit Note For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

The module is supplied from USB (optionally via unpopulated pin header).

Power Consumption

simpleViewer

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Typical Current Intel MAX 10 10M08 FPGA TBD*

* TBD - To Be Determined

Power Distribution Dependencies

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anchor Figure_PWR_PSPD title Power SequencyDistribution
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Voltage Monitor Circuit

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anchor	Figure_PWR_VMC
title	Voltage Monitor Circuit

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Power-On Sequence

There is no specific or special power-on sequence, just one single power source is needed. After power on, the green LED (D1) will be on.

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Power Rails

Voltage

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anchor Table_PWR_PR title Module power rails.
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Power Rail Name Connector Designator	VCC / VCCIO Schematic Name

J2 Pin	Connector J9 Pin	Direction	Notes
VIN	J2-13

VIN

-

5VInput

Input	5 V - Pin Header
3.3V

J2-12

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3.3V

	Output
5V

5V

J2-14

-

Output

J9

USB_VBUS	-

5V

J9-1

Input

5 V - USB Connector