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Scroll Title

anchor	Table_SIP_JTG
title	JTAG pins connection

Scroll Table Layout

On-board Peripherals

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hidden	true
id	Comments

Notes :

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anchor	Table_OBP_SPISDRAM
title	Quad SPI SDRAM interface MIOs IOs and pins

Scroll Table Layout

SDRAM I/O Signals	Signal Schematic Name	Connected to	Notes
Address inputs	A0 ... A13	bank 3	-
Bank address inputs	BA0 / BA1	bank 3	-
Data input/output	DQ0 ... DQ15	bank 6	-
Data mask	DQM0 ... DQM1	bank 6	-
Clock	CLK	bank 3
Control Signals	CS	bank 3	Chip select
	CKE	bank 3	Clock enable
	RAS	bank 3	Row Address Strobe
	CAS	bank 3	Column Address Strobe
	WE	bank 3	Write Enable

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