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anchor	Table_OBP_IOs
title	FPGA I/O Banks

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FPGA Bank	I/O Signal Count	Connected to	Notes
Bank 1A	7	1x14 Pin header, J1	AIN0...6
Bank 1A	1	Jumper, J3	AIN7
Bank 1B	5	1x6 Pin header, J4	JTAG_EN, TDI, TDO, TMS, TCK
Bank 2	4	1x14 Pin header, J1	D2...5
	5	A2D, U15	ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV
	1	12MHz Oscillator, U7	CLK12M
	2	Amplifier, U12	nIAMP_A0, nIAMP_A1
Bank 3	22	SDRAM, U2	RAM_ADDR_CMD
Bank 5	9	1x14 Pin header, J2	DIO6...14
	2	1x14 Pin header, J1	DIO0...1
	1	D12_R	DIO12
Bank 6	16	SDRAM, U2	DQ0...15
	2	SDRAM, U2	DQM0...1
	1	D11_R	DIO11
Bank 8	8	User Red LEDs, D2...9	LED0...7
	6	SPI Flash, U5	F_CS, F_CK, F_DI, F_DO, nSTATUS, DEVCLRn
	1	Red LED, D10	CONF_DONE
	6	FTDI JTAG/UART Adapter, U3	BDBUS0...5
	1	Push Button, S2	USER_BTN

JTAG Interface

JTAG access to the TEI0015 SoM through pin header connector J4.

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anchor	Table_OBP_SDRAM
title	SDRAM interface IOs and pins

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SDRAM I/O Signals	Signal Schematic Name	Connected to	Notes
Address inputs	A0 ... A13	bank 3	-
Bank address inputs	BA0 / BA1	bank 3	-
Data input/output	DQ0 ... DQ15	bank 6	-
Data mask	DQM0 ... DQM1	bank 6	-
Clock	CLK	bank 3
Control Signals	CS	bank 3	Chip select
	CKE	bank 3	Clock enable
	RAS	bank 3	Row Address Strobe
	CAS	bank 3	Column Address Strobe
	WE	bank 3	Write Enable

FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

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title	FTDI chip interfaces and pins

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FTDI Chip U3 Pin	Signal Schematic Name	Connected to	Notes
ADBUS0	TCK	FPGA bank 1B, pin G2	JTAG interface
ADBUS1	TDI	FPGA bank 1B, pin F5
ADBUS2	TDO	FPGA bank 1B, pin F6
ADBUS3	TMS	FPGA bank 1B, pin G1
BDBUS0	BDBUS0	FPGA bank 8, pin A4	user configurable
BDBUS1	BDBUS1	FPGA bank 8, pin B4	user configurable
BDBUS2	BDBUS2	FPGA bank 8, pin B5	user configurable
BDBUS3	BDBUS3	FPGA bank 8, pin A6	user configurable
BDBUS4	BDBUS4	FPGA bank 8, pin B6	user configurable
BDBUS5	BDBUS5	FPGA bank 8, pin A7	user configurable

SPI Flash Memory

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

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anchor	Table_OBP_QSPI
title	Quad SPI Flash memory interface

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Signal Schematic Name	Connected to	Notes
F_CS	FPGA bank 8, pin B3	chip select
F_CLK	FPGA bank 8, pin A3	clock
F_DI	FPGA bank 8, pin A2	data in / out
nSTATUS	FPGA bank 8, pin C4	data in / out, configuration dual-purpose pin of FPGA
DEVCLRN	FPGA bank 8, pin B9	data in / out, configuration dual-purpose pin of FPGA
F_DO	FPGA bank 8, pin B2	data in / out

EEPROM

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

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The TEI0010 board is equipped with the Analog Devices AD4003BCPZ, 18-bit A2D converter (ADC) and digital GPIO's can be operated at 20MHz.

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title	I2C EEPROM A2D converter interface MIOs and pins

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Schematic	Connected to	Notes

EECS

FTDI U3, Pin EECS

EECLK

FTDI U3, Pin EECLK

IN+	Diff Amplifier U14, VOUT-
IN-	Diff Amplifier U14, VOUT+
SDI	Bank 2, ADC_SDI
SDO	Bank 2, ADC_SDO
SCK	Bank 2, ADC_SCK
CNV	Bank 2, ADC_CNV

EEDATAFTDI U3, Pin EEDATA

Trenz Electronic Documentation

Versions Compared

Old Version 33

New Version 34

Key

JTAG Interface

FTDI FT2232H

SPI Flash Memory

EEPROM

LEDs