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anchor Table_OVOBP_RSTIOs title Reset process.FPGA I/O Banks
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Signal	B2B	I/O	Note

Signals, Interfaces and Pins

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Notes : For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example: SD USB ETH FMC ... For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example JTAG UART I2C MGT ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

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anchor	Table_SIP_B2B
title	General PL I/O to B2B connectors information

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true FPGA Bank I/O Signal Count Connected to Notes Bank 1A 7 1x14 Pin header, J1 AIN0...6 1 Jumper, J3 AIN7 Bank 1B 5 1x6 Pin header, J4 JTAG_EN, TDI, TDO, TMS, TCK Bank 2 4 1x14 Pin header, J1 D2...5 5 A2D, U15 ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV 1 12MHz Oscillator, U7 CLK12M 2 Amplifier, U12 nIAMP_A0, nIAMP_A1 Bank 3 22 SDRAM, U2 RAM_ADDR_CMD Bank 5 9 1x14 Pin header, J2 DIO6...14 2 1x14 Pin header, J1 DIO0...1 1 D12_R DIO12 Bank 6 16 SDRAM, U2 DQ0...15 2 SDRAM, U2 DQM0...1 1 D11_R DIO11 Bank 8 8 User Red LEDs, D2...9 LED0...7 6 SPI Flash, U5 F_CS, F_CK, F_DI, F_DO, nSTATUS, DEVCLRn 1 Red LED, D10 CONF_DONE 6 FTDI JTAG/UART Adapter, U3 BDBUS0...5 1 Push Button, S2 USER_BTN

JTAG Interface

JTAG access to the TExxxx TEI0015 SoM through B2B pin header connector JMXJ4.

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anchor Table_SIP_JTG title JTAG pins connection
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true JTAG Signal B2B Pin Header Connector Note TMS J4-6 TDI TDO J4-5 TDO J4-4 TCK J4-3 JTAG_EN

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J4-2

On-board Peripherals

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

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MIO Pin	Connected to	B2B	Notes
MIO12...14	SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK	J2	QSPI
Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchor Table_OBP_MIOs title MIOs pinsOn board peripherals
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MIO Pin	Connected to	B2B	Notes

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widths sortByColumn 1 sortEnabled false cellHighlighting true Chip/Interface Designator Notes SDRAM U2 FTDI FT2232H U3 JTAG/UART Adapter SPI Flash Memory U5 EEPROM U9 Oscillator U7 12MHz clock source A2D Convertor U12, U14 Analog to Digital Convertor 8x User LEDs D2...9 Red LEDs

SDRAM

TEI0015 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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hidden true id Comments
Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

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hidden true id Comments
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchor	Table_OBP
title	On board peripherals

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Quad SPI Flash Memory

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id	Comments

Notes :

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Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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anchor Table_OBP_SDRAM title SDRAM interface IOs and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true SDRAM I/O Signals Signal Schematic Name Connected to Notes Address inputs A0 ... A13 bank 3 - Bank address inputs BA0 / BA1 bank 3 - Data input/output DQ0 ... DQ15 bank 6 - Data mask DQM0 ... DQM1 bank 6 - Clock CLK bank 3 Control Signals CS bank 3 Chip select CKE bank 3 Clock enable RAS bank 3 Row Address Strobe CAS bank 3 Column Address Strobe WE bank 3 Write Enable

FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

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anchor Table_OBP_SPIFTDI title Quad SPI interface MIOs FTDI chip interfaces and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MIO FTDI Chip U3 Pin Signal Schematic U?? Pin Name Connected to Notes

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anchor	Table_OBP_RTC
title	I2C interface MIOs and pins

ADBUS0 TCK FPGA bank 1B, pin G2 JTAG interface ADBUS1 TDI FPGA bank 1B, pin F5 ADBUS2 TDO FPGA bank 1B, pin F6 ADBUS3 TMS FPGA bank 1B, pin G1 BDBUS0 BDBUS0 FPGA bank 8, pin A4 user configurable BDBUS1 BDBUS1 FPGA bank 8, pin B4 user configurable BDBUS2 BDBUS2 FPGA bank 8, pin B5 user configurable BDBUS3 BDBUS3 FPGA bank 8, pin A6 user configurable BDBUS4 BDBUS4 FPGA bank 8, pin B6 user configurable BDBUS5 BDBUS5 FPGA bank 8, pin A7 user configurable

SPI Flash Memory

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

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anchor Table_OBP_I2C_RTCQSPI title I2C Address for RTCQuad SPI Flash memory interface
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MIO Pin	I2C Address	Designator	Notes

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anchor	Table_OBP_EEP
title	I2C EEPROM interface MIOs and pins

Signal Schematic Name Connected to Notes F_CS FPGA bank 8, pin B3 chip select F_CLK FPGA bank 8, pin A3 clock F_DI FPGA bank 8, pin A2 data in / out nSTATUS FPGA bank 8, pin C4 data in / out, configuration dual-purpose pin of FPGA DEVCLRN FPGA bank 8, pin B9 data in / out, configuration dual-purpose pin of FPGA F_DO FPGA bank 8, pin B2 data in / out

EEPROM

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

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anchor Table_OBP_I2C_EEPROMEEP title I2C address for EEPROM interface MIOs and pins
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MIO Pin	I2C Address	Designator	Notes

LEDs

Schematic Connected to Notes EECS FTDI U3, Pin EECS EECLK FTDI U3, Pin EECLK EEDATA FTDI U3, Pin EEDATA

A2D Convertor

The TEI0010 board is equipped with the Analog Devices AD4003BCPZ, 18-bit A2D converter (ADC).

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anchor Table_OBP_LEDA2D title On-board LEDsA2D converter interface and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Schematic Pins	Color

Connected to

Active Level

Notes

Note