Page History

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Template Revision 2.6 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

HTML
<!-- Template Revision 1.0 Basic Notes - export PDF to download, if vivado revision is changed! - Template is for different design and SDSoC and examples, remove unused or wrong description! -->

Scroll Only (inline)
Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

Scroll pdf ignore

Overview

HTML
<!-- General Design description -->

Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.

Key Features

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<!-- Add Basic Key Features of the design (should be tested) -->

Excerpt
QSPI SDK Custom Carrier (minimum PS Design with available module components only) Special FSBL for QSPI Programming

Revision History

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<!-- - Add changes from design - Export PDF to download, if vivado revision is changed! -->

...

new assembly variant

...

new assembly variant

...

additional notes for FSBL generated with Win SDK
changed *.bif

...

new assembly variant

...

bugfix TE0803-01-04EG boart part file

...

new assembly variant

...

new assembly variant

...

new assembly variant

...

rework Board Part Files

...

Update Board Part CSV File with new Flash assembly variants

...

2017-11-14

...

Initial release

Release Notes and Know Issues

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<!-- - add known Design issues and general Notes for the current revision -->

...

Requirements

Software

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<!-- Add needed external Software -->

...

Hardware

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<!-- Hardware Support -->

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this boart part files are not used for this reference design. * Only different Flash size.

Design supports following carriers:

...

Additional HW Requirements:

...

Content

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<!-- Remove unused content -->

For general structure and of the reference design, see Project Delivery

Design Sources

...

tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>

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Important General Note:

Export PDF to download, if vivado revision is changed!

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template (note: inner scroll ignore/only only with drawIO object):

Scroll Title

anchor	Figure_xyz
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, use

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
Scroll Title
anchor Table_xyz
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
style
widths
sortByColumn 1
sortEnabled false
cellHighlighting true
Example Comment
1 2

...

Scroll pdf ignore

Overview

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Notes :

short description of the design
Short Link of "Scroll only" macro:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.

Refer to http://trenz.org/te0803-info for the current online version of this manual and other available documentation.

Key Features

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hidden	true
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Notes :

Add basic key futures, which can be tested with the design

Excerpt
Vivado 2018.3 QSPI SDK Custom Carrier (minimum PS Design with available module components only) Modified FSBL (some additional outputs only) Special FSBL for QSPI Programming

Revision History

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id	Comments

Notes :

add every update file on the download
add design changes on description

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anchor	Table_DRH
title	Design Revision History

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Date	Vivado	Project Built	Authors	Description
2019-5-06	2018.3	TE0803-test_board_noprebuilt-vivado_2018.3-build_05_20190506161948.zip TE0803-test_board-vivado_2018.3-build_05_20190506161936.zip	John Hartfiel	custom FSBL new assembly variants
2018-10-26	2018.2	TE0803-test_board_noprebuilt-vivado_2018.2-build_03_20181026141705.zip TE0803-test_board-vivado_2018.2-build_03_20181026141651.zip	John Hartfiel	new assembly variant
2018-08-14	2018.2	TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180814103119.zip TE0803-test_board-vivado_2018.2-build_02_20180814103105.zip	John Hartfiel	new assembly variant
2018-07-13	2018.2	TE0803-test_board_noprebuilt-vivado_2018.2-build_02_20180713085721.zip TE0803-test_board-vivado_2018.2-build_02_20180713085704.zip	John Hartfiel	additional notes for FSBL generated with Win SDK changed *.bif
2018-05-17	2017.4	TE0803-test_board_noprebuilt-vivado_2017.4-build_09_20180517152118.zip TE0803-test_board-vivado_2017.4-build_09_20180517152103.zip	John Hartfiel	new assembly variant
2018-04-11	2017.4	TE0803-test_board_noprebuilt-vivado_2017.4-build_07_20180411081821.zip TE0803-test_board-vivado_2017.4-build_07_20180411081757.zip	John Hartfiel	bugfix TE0803-01-04EG boart part file
2018-02-13	2017.4	TE0803-test_board_noprebuilt-vivado_2017.4-build_06_20180213120257.zip TE0803-test_board-vivado_2017.4-build_06_20180213120229.zip	John Hartfiel	new assembly variant
2018-02-05	2017.4	TE0803-test_board-vivado_2017.4-build_05_20180205101915.zip TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180205101943.zip	John Hartfiel	new assembly variant
2018-01-31	2017.4	TE0803-test_board-vivado_2017.4-build_05_20180131124202.zip TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180131124215.zip	John Hartfiel	new assembly variant
2018-01-18	2017.4	TE0803-test_board-vivado_2017.4-build_05_20180118160549.zip TE0803-test_board_noprebuilt-vivado_2017.4-build_05_20180118160604.zip	John Hartfiel	rework Board Part Files
2017-11-16	2017.2	TE0803-test_board-vivado_2017.2-build_05_20171116152716.zip TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171116154619.zip	John Hartfiel	Update Board Part CSV File with new Flash assembly variants
2017-11-14	2017.2	TE0803-test_board-vivado_2017.2-build_05_20171114090712.zip TE0803-test_board_noprebuilt-vivado_2017.2-build_05_20171114090725.zip	John Hartfiel	Initial release

Release Notes and Know Issues

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Notes :

add known Design issues and general notes for the current revision
do not delete known issue, add fixed version time stamp if issue fixed

Issues	Description	Workaround	To be fixed version
No known issues	---	---	---

Requirements

Software

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Notes :

list of software which was used to generate the design

Software	Version	Note
Vivado	2018.3	needed
SDK	2018.3	needed

Hardware

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Notes :

list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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anchor	Table_HWM
title	Hardware Modules

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Module Model	Board Part Short Name	PCB Revision Support	DDR	QSPI Flash	EMMC	Others	Notes
TE0803-ES1	es1_2gb	REV01	2GB	64MB	NA	NA	Not longer supported by vivado
TE0803-01-02EG-1E	2eg_2gb	REV01	2GB	64MB	NA	NA	NA
TE0803-01-02CG-1E	2cg_2gb	REV01	2GB	64MB	NA	NA	NA
TE0803-01-03EG-1E	3eg_2gb	REV01	2GB	64MB	NA	NA	NA
TE0803-01-03CG-1E	3cg_2gb	REV01	2GB	64MB	NA	NA	NA
TE0803-01-02EG-1EA	2eg_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-02CG-1EA	2cg_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-03EG-1EA	3eg_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-03CG-1EA	3cg_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-02-03EG-1EB	3eg_4gb	REV02\|REV01	4GB	128MB	NA	NA	NA
TE0803-01-04CG-1EA	4cg_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-04EV-1EA	4ev_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-04EV-1E3	4ev_2gb	REV01	2GB	128MB	NA	1 mm connectors	NA
TE0803-01-04EG-1EA	4eg_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-04CG-1EB	4cg_2gb	REV01	2GB	256MB	NA	NA	NA
TE0803-01-05EV-1EA	5ev_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-01-05EV-1IA	5ev_i_2gb	REV01	2GB	128MB	NA	NA	NA
TE0803-02-04EV-1EB	4ev_4gb	REV02	4GB	128MB	NA	NA	NA
TE0803-02-04EV-1E3	4ev_4gb	REV02	4GB	128MB	NA	1 mm connectors	NA
TE0803-02-04EG-1E3	4eg_4gb	REV02	4GB	128MB	NA	1 mm connectors	NA
TE0803-03-2AE11-A	2cg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-2BE11-A	2eg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-3AE11-A	3cg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-3BE11-A	3eg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-4AE11-A	4cg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-4BE11-A	4eg_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-4BE21-L	4eg_4gb	REV03	4GB	128MB	NA	1 mm connectors	NA
TE0803-03-4BI21-A	4eg_i_4gb	REV03	4GB	128MB	NA	NA	NA
TE0803-03-4DE11-A	4ev_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-4DE21-L	4ev_4gb	REV03	4GB	128MB	NA	1 mm connectors	NA
TE0803-03-4GE21-L	4eg_2_4gb	REV03	4GB	128MB	NA	1 mm connectors	NA
TE0803-03-5DE11-A	5ev_2gb	REV03	2GB	128MB	NA	NA	NA
TE0803-03-5DI21-A	5ev_i_4gb	REV03	4GB	128MB	NA	NA	NA

Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this boart part files are not used for this reference design.

Design supports following carriers:

Scroll Title

anchor	Table_HWC
title	Hardware Carrier

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Carrier Model	Notes
Custom PCB	use simple Board Part files, if MIO connected is different to TEBF0808
TEBF0808	Used as reference carrier.
TEBT0808-01	Change UART0 to UART1 (MIO68...69) and regenerate design

Additional HW Requirements:

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anchor	Table_AHW
title	Additional Hardware

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orientation	portrait
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repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Additional Hardware	Notes
---	---

Content

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Notes :

content of the zip file

For general structure and of the reference design, see Project Delivery

Design Sources

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anchor	Table_DS
title	Design sources

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orientation	portrait
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repeatTableHeaders	default
style
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sortEnabled	false
cellHighlighting	true

Type	Location	Notes
Vivado	<design name>/block_design <design name>/constraints <design name>/ip_lib	Vivado Project will be generated by TE Scripts
SDK/HSI	<design name>/sw_lib	Additional Software Template for SDK/HSI and apps_list.csv with settings for HSI

Additional Sources

Scroll Title

anchor	Table_ADS
title	Additional design sources

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Type	Location	Notes
---	---	---

Prebuilt

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Notes :

prebuilt files

Template Table:

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anchor	Table_PF
title	Prebuilt files

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orientation	portrait
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repeatTableHeaders	default
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sortEnabled	false
cellHighlighting	true

File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image	*.img	Debian Image for SD-Card
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
SREC-File	*.srec	Converted Software Application for MicroBlaze Processor Systems

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anchor	Table_PF
title	Prebuilt files (only on ZIP with prebult content)

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orientation	portrait
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repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Additional Sources

...

Prebuilt

HTML

File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdf	Exported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Important set new Vivado version link on every Design update of new vivado version!
Set Link to download folder (Remove ../de/.. ../en/.. from url) for example

HTML

<!-- Add correct path

: https://shop.trenz-electronic.de/

en/

Download/?path=Trenz_Electronic

/TE0803

/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/

2017

2018.

1/Starterkit -->

2/test_board

Reference Design is available on:

TE0803 "Test Board" Reference Design

Design Flow

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Notes :

Basic Design Steps
Add/ Remove project specific description

HTML

Note
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

Launch

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Note:

Programming and Startup procedure

Programming

Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0808
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP

SD

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with SDK Debugger into device, see:

Usage

QSPI Boot:

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select QSPI Card as Boot Mode
Note: See TRM of the Carrier, which is used.
Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from QSPI into OCM, 2. FSBL loads Application into DDR

Debugging:

System Design - Vivado

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Note:

Description of Block Design, Constrains... BD Pictures from Export...

Block Design

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anchor	Figure_BD
title	Block Design

Image Added

PS Interfaces

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Note:

optional for Zynq / ZynqMP only
add basic PS configuration

Activated interfaces:

Scroll Title

anchor	Table_PSI
title	PS Interfaces

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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Type	Note
DDR
QSPI	MIO
UART0	MIO, please select other one, if you have connected uart to second controller or other MIO
SWDT0..1
TTC0..3

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - SDK/HSI

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hidden	true
id	Comments

Note:

optional chapter separate
sections for different apps

For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

zynqmp_fsbl

TE modified 2018.3 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device Name

zynqmp_fsbl_flash

TE modified 2018.3 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Image Removed
Press 0 and enter for minimum setup
(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
Create Project
1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
  Note: Select correct one, see TE Board Part Files
  Important: Use Board Part Files, which did not ends with *_tebf0808
Create HDF and export to prebuilt folder
1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
  Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
Generate Programming Files with HSI/SDK
1. Run on Vivado TCL: TE::sw_run_hsi
  Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
  Note: See SDK Projects

Launch

Programming

HTML
<!-- Description of Block Design, Constrains... BD Pictures from Export... -->

Note
Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

HTML

<!--
Example:
Connect JTAG and power on PCB
(if not done) Select 
correct device and Xilinx install path on "design_basic_settings.cmd" 
and create Vivado project with "vivado_create_project_guimode.cmd" or 
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

   -->

Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0808
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP

SD

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with SDK Debugger into device, see:

Usage

QSPI Boot:

Prepare HW like described on section Programming
Connect UART USB (most cases same as JTAG)
Select QSPI Card as Boot Mode
Note: See TRM of the Carrier, which is used.
Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from QSPI into OCM, 2. FSBL loads Application into DDR

Debugging:

System Design - Vivado

HTML
<!-- Description of Block Design, Constrains... BD Pictures from Export... -->

Block Design

Image Removed

PS Interfaces

Activated interfaces:

...

Constrains

Basic module constrains

Code Block

language	ruby
title	_i_bitgen.xdc

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - SDK/HSI

HTML
<!-- optional chapter separate sections for different apps -->

For SDK project creation, follow instructions from:

SDK Projects

Application

zynqmp_fsbl

Xilinx default FSBL

zynqmp_fsbl_flash

TE modified 2017.4 FSBL

...

- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

...

hello_te0803

Hello TE0803 is a Xilinx Hello World example as endless loop instead of one console output.

Additional Software

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id	Comments

Note:

Add description for other Software, for example SI CLK Builder ...
SI5338 and SI5345 also Link to:
- Si5345
- Si5338

HTML

No additional software is needed.

...

To get content of older revision got to "Change History" of this page and select older document revision number.

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id	Comments

Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

HTML

Date

Document Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

	current-version
	current-version
prefix	v.

Page info

	modified-user
	modified-user

Release 2018.3

2018-10-26

v.18

John Hartfiel

new assembly variant

2018-08-14

Aug 2018

v.16

John Hartfiel

new assembly variant

2018-07-13

Jul 2018

v.15

John Hartfiel

Release 2018.2

17

May

2018-05-18

v.14

John Hartfiel

new assembly variant

2018-04-11

Apr 2018

v.13

John Hartfiel

bugfix boart part file

2018-04-03

Apr 2018

v.11

John Hartfiel

new assembly variant

2018-01-18

v.6

John Hartfiel

Release 2017.4

2017-11-16

v.4

John Hartfiel

Update assembly versions with new Flash size

2017-11-14

v.3

John Hartfiel

Release 2017.2

All

Page info

	modified-users
	modified-users

...

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 18

New Version 19

Key

Table of contents

Overview

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Content

Design Sources

Table of contents

Overview

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Content

Design Sources

Additional Sources

Prebuilt

Additional Sources

Prebuilt

Download

Design Flow

Launch

Programming

QSPI

SD

JTAG

Usage

System Design - Vivado

Block Design

PS Interfaces

Constrains

Basic module constrains

Design specific constrain

Software Design - SDK/HSI

Application

zynqmp_fsbl

zynqmp_fsbl_flash

Launch

Programming

QSPI

SD

JTAG

Usage

System Design - Vivado

Block Design

PS Interfaces

Constrains

Basic module constrains

Design specific constrain

Software Design - SDK/HSI

Application

zynqmp_fsbl

zynqmp_fsbl_flash

hello_te0803

Additional Software