Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
B2B Connector | Interfaces | Number of I/O | Notes |
---|
J1
| User I/O | 22 singel ended, 11 Differential 8 singel ended, 4 Differential 8 singel ended, 4 Differential 8 singel ended, 4 Differential 3 singel ended | Connected to Bank 66 Connected to Bank 228 Connected to Bank 229 Connected to Bank 230 VCCO_66, PL_1V8 | J2
| Ethernet PHY | 32 singel ended, 16 Differential 4 singel ended, 16 Differential | Connected to Bank 505 Connected to Bank 128 | Control Signals | 15 single ended | PLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE | Power Control Signal | 10 single ended | EN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L | JTAG Interface | 7 single ended | TCK, TDI, TMS, TDO, MR, Rxd, Txd | WANNE2 | 2 single ended | PLL_SCL, PLL_SDA | Clock | 6 singel ended, 3 Differential | CLK0, CLK7, CLK8 | J3
| User I/O | 12 singel ended, 6 Differential 12 singel ended, 6 Differential | Connected to Bank 48 Connected to Bank 47 | Clock | 6 singel ended, 3 Differential | CLK228, CLK229, CLK230 | PJTAG Interface | 7 single ended | PJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO, | MIO | 27 single ended | MIO19..76 | UART | 2 single ended | TXD, RXD | Power pins | 4 single ended | PS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47 | J4 | User I/O | 48 singel ended, 62 Differential 4 single ended | Connected to Bank 64 Connected to Bank 64 | Power pins | 4 single ended | VCCO_64, VCCO65 |
|