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some sources available on public doc TEBT0808 TRM

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Template Revision 2.5

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

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The Trenz Electronic TEBT0808 -01 is a testboard for module TE0808 (REV 02 and 03) as well as for TE0803 (REV 01)test fixture for module TE080x series.

Refer to http://trenz.org/tebt0808-info for the current online version of this manual and other available documentation.

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Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

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  • Single 3.3V input (Direct modules power supply)
  • Header for TE0790 JTAG/UART Adapter
  • 20 Pin ARM JTAG header (connected to MIO JTAG 0)
  • 10 Pin I2C header for Silabs Clock Builder Field Programmer
  • Done, Error/Status LEDs
  • One PL GT with SMA connectors
  • One PS GT with SMA connectors
  • GT local loopback
  • PL I/O loopbacks
  • PS I/O loopbacks
  • Boot Mode switches
  • Power control switches to control TE0808 TE080x power domains
  • One pre-assembled TE0790 XMOD FTDI JTAG adapter

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Scroll Title
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titleTEBT0808 block diagram


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titleBoot process.

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M3M2M1M0Bootmode HexBootmodeNotes
ONONONON0x0PS Main JTAG (TE0790 USB JTAG)Needed for SPI Flash Programming
ONONOFFON0x2SPI Flash (dual parallel, 4bit x 2, 32bit Addressing)Default
ONOFFOFFOFF0x8PJTAG(MIO29:26)



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titleReset process.

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Signal

B2BNote

PLL_RST

J2-89
SRST_BJ2-96connected to PJTAG0_SRST - J16


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titleGeneral PL I/O to B2B connectors information

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B2B ConnectorInterfacesNumber of I/ONotes
J1

User I/O

22 singel ended, 11 Differential

8 singel ended, 4 Differential

8 singel ended, 4 Differential

8 singel ended, 4 Differential

3 singel ended

Connected to Bank 66

Connected to Bank 228

Connected to Bank 229

Connected to Bank 230

VCCO_66, PL_1V8

J2

Ethernet PHY

32 singel ended, 16 Differential

4 singel ended, 16 Differential

Connected to Bank 505

Connected to Bank 128

Control Signals15 single endedPLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE
Power Control Signal10 single endedEN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L
JTAG Interface7 single endedTCK, TDI, TMS, TDO, MR, Rxd, Txd
WANNE22 single endedPLL_SCL, PLL_SDA
Clock

6 singel ended, 3 Differential

CLK0, CLK7, CLK8

J3



User I/O

12 singel ended, 6 Differential

12 singel ended, 6 Differential

Connected to Bank 48

Connected to Bank 47

Clock6 singel ended, 3 DifferentialCLK228, CLK229, CLK230
PJTAG Interface7 single endedPJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO,
MIO27 single endedMIO19..76
UART2 single endedTXD, RXD
Power pins4 single endedPS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47
J4User I/O

48 singel ended, 62 Differential

4 single ended

Connected to Bank 64

Connected to Bank 64

Power pins4 single endedVCCO_64, VCCO65



XMOD JTAG

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JTAG access to the TE0803 or TE0808 SoM TE080x  UltraSoM+ through B2B connector JM2.

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anchorTable_SIP_JTG
titleJTAG pins connection

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JTAG Signal

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B2B Connector

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J2-120

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On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

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Notes :

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TODO XMOD Pin Header and recommended XMOD DIP setting and used MIO on B2B connector


PJTAG

TODO Pin Header

SI I2C Pinheader

TODO Pin Header

SMA

TODO Pin Header

Test Points

TODO List of all Test points with connection

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
OscillatorU2125.00 MHz



DIP Switch

There are thre DIP Switches, S1, S2, S3.

The Boot Mode can be set through DIP Switch S1, refer to BootMode table.

Designator
Scroll Title
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titleOn board peripheralsDIP Switch S1

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Signals
Chip/Interface

B2B

S1 switchNotes
Oscillator
MODE0
U2125.00 MHz

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There are thre DIP Switches, S1, S2, S3.

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J2-109S1A
MODE1J2-107S1B
MODE2J2-105S1C
MODE3J2-103S1D


Control signals must be set by DIP Switch S2, S3.

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titleDIP Switch S1S2

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SignalsB2BS1 S2 switchNotes
MODE0EN_PSGTJ2-10984S1AS2A
EN_GT_RMODE1J2-10795S1BS2B
EN_GT_LMODE2J2-10597S1CS2C
EN_PLL_PWRMODE3J2-10377S1D

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S2Dconnected to PG_PL



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titleDIP Switch S2S3

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connected to PG_PL
SignalsB2BS2 S3 switchNotes
EN_PSGTDDRJ2-84112S2AS3A
EN_GT_RLPDJ2-95108S2BS3B
EN_GT_LPLJ2-97101S2CS3C
EN_PLL_PWRFPDJ2-77102S2DS3D


LEDs

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titleDIP Switch S3On-board LEDs

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DesignatorSignalsColorB2BS3 switchNotesEN_DDRJ2-112S3AEN_LPDJ2-108S3BEN_PLJ2-101S3CEN_FPDJ2-102S3D

LEDs

Connected toActive LevelNote
D2RedDONELow
D3RedERR_STATUSLow
D4RedERR_OUTLow


Clock Sources

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titleOn-board LEDsOsillators

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DesignatorColorDescriptionConnected toFrequencyActive LevelNote
D2U2RedDONELowD3RedERR_STATUSLowD4RedERR_OUTLow

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MEMS Oscillator125.00 MHz


Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Scroll Title
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titleOsillatorsPower Consumption

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Frequency
DesignatorDescription2,0mm MC LB2NoteU2MEMS Oscillator125.00 MHz

Power and Power-On Sequence

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hiddentrue
idComments

In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

J73.3V direct modules power supply
J8GND


Current depends manly on design and cooling solution. Use Xilinx Power Estimator and/or Your Vivado Project to estimate min current. Minimum of 3A are recommanded for basic functionality.

Power Consumption

Current depends manly on design and cooling solution. Use Xilinx Power Estimator and/or Your Vivado Project to estimate min current. Minimum of 3A are recommanded for basic functionality.

Scroll Title
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titlePower Consumption

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Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies

Input oower sourced directly the module, Only one Diode D1 is used for protection.

Power Supply

TestKits are pre-assembled and pre-flashed with initial Flash image, they start up as soon as power (3.3V) is applied.

Power Consumption

Scroll Title
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titlePower ConsumptionDistribution


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Power Input PinTypical Current
VINTBD*

* TBD - To Be Determined

Power Distribution Dependencies

If you connect the power supply with wrong polarity, Diod D1 protects the board not to be damaged. 

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anchorFigure_PWR_PD
titlePower Distribution
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Power Rails

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titleModule power rails.

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Power Rail Name

B2B

JM1 Pin

B2B

JM2 Pin

B2B

JM3 Pin

B2B

JM4 Pin

DirectionNotes
3.3V151,153,155,157,159140,142,144,146,156,158,160,
153,155,157,159
157,158,159,160-OutputCarrier power supply to module power rails PL_DCDCIN. DCDCIN, LP_DCDC, GT_DCDC, PL_3V3V

VCCO_47

--43, 44-OutputConnected to 1.8 (SI_PLL_1V8)
VCCO_48--15,16-OutputConnected to 1.8 (SI_PLL_1V8)
VCCO_64---58, 106OutputConnected to 1.8 (PL_1V8)
VCCO_65---69, 105OutputConnected to 1.8 (PL_1V8)

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Power Rails

Notes
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titleModule power rails.
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Power Rail Name

B2B

JM1 Pin

B2B

JM2 Pin

B2B

JM3 Pin

B2B

JM4 Pin

Direction
VCCO_6690,120---OutputConnected to 1.8 (PL_1V8)
3.3V
PS_1V8-
138...160
99,147, 148
-
-Input
PS

PLL_
BATT
3V3-
125
-
-
152-Output
Connected to 1.8 (PS_1V8)

VCCO_47

--43, 44-OutputConnected to SI_PLL_1V8VCCO_48Connected to
3.3V
PL_1_V8121,121---
15,16-Output
Input1.8V for PL Banks
SI_PLL
_1V8PS
_1V8--
147, 148
151-
OutputPLL_3V3
Input
DDR 1V2-135-
152
-
Output3.3VVCCO_64
Inout
PL_3V3--152-
58,106
OutputConnected to
1.8 (PL_1V8)VCCO_65
3.3V
PSBAT-125--
69,105Output
Output1.2V..1.5V, abs. max 2V
Connected to 1.8 (PL_1V8)


Board to Board Connectors

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titlePS absolute maximum ratings

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SymbolsMinMaxUnitNote
VIN-03.34V

Limit by DC1123,

Note: VIN is connected directly to module, this is not considered here

Input Supply Voltage

Storage Temperatur-40+85°C


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Scroll Title
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titleRecommended operating conditions.

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SymbolsMinMaxUnitNote
VIN03,143.347VInput Supply VoltageStorage Temperatur-40+85°CImportant, check also TRM of the connected module


Physical Dimensions

  • Module size: 90 mm × 90 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 3.5 mm.

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Scroll Title
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titleTrenz Electronic Shop Overview

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Trenz shop TE0728 TEBT0808 overview page
English pageGerman page


Revision History

Hardware Revision History

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titleHardware Revision History

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DateRevisionChanges
2016-ß6-2901-


Document Change History

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