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Table of Contents

Table of Contents

Overview

The Cyclone10 Cyclone 10 LP Reference Kit is the world's first development board with a 55kLE 55 kLE (Logic Elements) Intel Cyclone 10 LP and a variety of interfaces for numerous applications. The board is comprehensively tested and ready for use with end products and can also be ordered in customer-specific variants according to your requirements.

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Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

  • Intel® Intel Cyclone 10 LP  LP [10CL055YU484C8G],
    • Package: UBGA-484
    • Speed Grade: 8 (Slowest)
    • Temperature: 0°C ~ 85°C 0 °C to 85° C
    • Package compatible device 10CL016, 10CL040, 10CL055, 10CL080 as assembly variant on request is possible
  • 16 MBit flash memory (2 MByte) Flash Memory (optional up to 32 MBit possibleMBit (4 MByte))
  • Integrated USB2.0 USB-JTAG Programmer
  • Pin Header connectorsConnectors
  • 256 64 MBit (8 MByte) SDRAM (optional up to 512 MBit possible(64 MByte)) SDRAM
  • 128 64 MBit (optional up to 512 MBit possible8 MByte) User Quad-SPI Flash memoryMemory (optional up to 128 MBit (16 MByte))
  • 64 MBit (8 MByte) HyperRAM (Pseudo SRAM) (optional up to 128 MBit possible(16 MByte))
  • FTDI - System Controller (CPLD)
  • 2x MAC address Address EEPROM
  • 2x Fast Ethernet PHY (10/100 Mbps)
  • 8-channelChannel, 12-bitBit, configurable ADC/DAC with on-chip reference
  • D-Sub connectorConnector
  • 2x RJ45 connectorConnector
  • LEDs:
    • Status LEDs, Power LED
    • 13x User LEDs
    • 7-segment displaySegment Display
  • Push bottunsButtons:
    • 2x Reset Push buttonsButtons
    • 5x User Push buttonsButtons
  • I/O: 70 GPIO: 321
  • LVDS: 132
  • 5 V Power Supply: 
  • 5 V

  • Dimension: 95 mm x 110 mmMinimum 1A
  • Others:
    • Reverse polarity of supply voltage protectionUnder/Over voltage protectionSupply Protection
    • Undervoltage/Overvoltage Protection

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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titleTEI0009 block diagramBlock Diagram


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Main Components

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titleTEI0009 main componentsMain Components


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  1. Barrel Power Jack, J12
  2. RJ45 socketSocket, J8...9
  3. D-Sub Connector, J11
  4. Push buttonButton (Reset), S7
  5. Grove connectorConnector, J5
  6. Under/Over Voltage ProtecterUndervoltage/Overvoltage Protector, U9
  7. 7-segment Segment LED, D11
  8. 1x6 pin headerPin Header, J4
  9. 1x8 pin headerPin Header, J2...3
  10. 8x User LEDs (Red LEDs), D2...9
  11. 8x 5x User LEDs (Red LEDs), D13...17
  12. 5x User Push buttonsButtons, S1 - S3...6
  13. Red LED (CONF_DONE), D10
  14. PSRAM memoryMemory, U3
  15. SDRAM memoryMemory, U10
  16. Voltage Regulator, U5U4 - U7
  17. AD/DA ConvertorConverter, U2
  18. Pmod 2x6 SMD host socket6x Pmod Host Socket, P1...6
  19. Intel ® Cyclone 10 LP, U1
  20. Serial Configuration memoryMemory, U5
  21. 1x10 pin headerPin Header, J1
  22. EEEPROMEEPROM, U15 - U18 - U20
  23. FTDI USB2 USB 2 to JTAG/UART adapterConverter, U14
  24. Micro USB 2.0 (receptacle) , J10
  25. Push button Button (RST_GPIO), S2
  26. Oscillator, U22
  27. Ethernet PHY, U17 - U19
  28. QSPI Flash memoryMemory, U12

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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titleInitial delivery state of programmable devices Delivery State of Programmable Devices on the moduleModule

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Storage device name

Content

Notes

QSPI Flash (U12)

Not programmed


EEPROM (U15)Programmed

FTDI configurationConfiguration

EEPROM (U18, U20)SDRAMNot programmedPSRAMExcept Ethernet MAC
SDRAM (U10)Not programmedFTDI System Controller CPLD


PSRAM (U3)Not programmed
Serial Configuration Memory (U5)Demo DesignProgrammed


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

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MODE Signal State

MSEL0MSEL1MSEL2MSEL3Connected to Boot Mode

MSEL[0:3]

0100Bank 6

AS (Active Serial)

RESET pin can be set through the push button S1.



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titleReset process.Process

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Signal

Connected to Note

RESET

S7 (Push button)S7, Push ButtonConnected to nCONFIGRST_GPIOS2 (Push button)EXT_RST

J3 (1x8 pin header)

Bank 2.


Signals, Interfaces and Pins

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FPGA bank number and number of I/O signals connected to the B2B connectorconnectors:

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titleGeneral PL I/O to B2B connectors informationPin Header and Pmod Connectors Information

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FPGA BankConnector I/O Signal CountVoltage LevelNotes
Bank 1J1 (Pin header)8 Single ended3.3 V
J2 (Pin header)8 Single ended3.3 V
J4 (Pin header)6 Single ended3.3 V
Bank 2

J3 (Pin header)

1 Single ended3.3 V
P1 (PMod SMD host socketPmod Host Socket)8 Single ended3.3 V
P2 (PMod SMD host socketPmod Host Socket)8 Single ended3.3 V
J11 (VGA host Host Socket)14 Single ended3.3 V
Bank 6J5 (Grove connectorConnector)2 Single ended3.3 V
Bank 7P5 (PMod SMD host socketPmod Host Socket)8 Single ended3.3 V
P6 (PMod SMD host socketPmod Host Socket)8 Single ended3.3 V
Bank 8P3 (PMod SMD host socketPmod Host Socket)8 Single ended3.3 V
P4 (PMod SMD host socketPmod Host Socket)8 Single ended3.3 V

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Pmod Host Socket

TEI0009 has 6 PMod 2x6 SMD Host Socket 90° 6 Pmod 2x6 host sockets which are connected to Cyclon 10 LP (U1).

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titlePMod SMD host socket informationPmod SMD Host Socket Information

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DesignatorSignalsConnected to Notes
P1P1_IO1...8Bank 2
P2P2_IO1...8Bank 2
P3P3_IO1...8Bank 8
P4P4_IO1...8Bank 8
P5P5_IO1...8Bank 7
P6P6_IO1...8Bank 7

UART Interface

UART access to TEI0009 is available on 1x8 pin header J2. 

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Pin Header

TEI0009 has 5 pin headers. The pin headers J1...4 are usable for Arduino modules, too.

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Schematic
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Pin Header J1SignalsConnected to 
Voltage Level
Notes
TXDJ2
J1 - 1...6D8...13Bank 1
3.3 VRXD

J1 - 7GND

J1 - 8AREFADC/DAC
J1 - 9D14_SDA
J2
Bank 1
3.3 V

Micro USB2.0 Connector

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J1 - 10D14_SCLBank 1



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titleMicro USB2.0 B Receptacle 90 ° informationPin Header J2

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Pin Header J2Signals
Schematic
Connected to 
Voltage LevelNotesUSB_VBUSGNDD-U14 (FTDI FT2232)3.3 VD+U14 (FTDI FT2232)3.3 V

RJ45 Connectors

TEI0009 is equipped with two RJ45 connectors and two Ethernet PHYs. RJ45 connectors J8 and J9 are connected to Ethernet PHYs U17 and U19 respectively. .

Notes
J2 - 1D0_RXDBank 1
J2 - 2D1_TXDBank 1
J2 - 3...8D2...4Bank 1



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titleRJ45 connectors informationPin Header J3

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Pin Header J3
Schematic
Signals
ETH1 PinETH2 PinNotesTD+ETH_TX_PU17- TXPU19- TXP
CTETH_CTREF_TCT--Connected to GND
TD-ETH_TX_NU17- TXMU19- TXMRD+ETH_RX_PU17- RXPU19- RXP
CTETH_CTREF_RCT--Connected to GND
RD-ETH_RX_NU17- RXMU19- RXMLED GreenETH_LED0U17- NWAYENU19- NWAYENLED YellowETH_LED1U17- SPEEDU19- SPEED

D-Sub Connectors

TEI0009 is equipped with a D-Sub connector (Receptacle) which provides interface to Cyclone 10 LP through Bank 2.

Connected to Notes
J2 - 1NC-
J3 - 23.3V3.3 V
J3 - 3EXT_RSTBank 2Pulled-up to 3.3 V
J3 - 43.3V3.3 V
J3 - 55V5 V
J3 - 6...7GNDGND
J2 - 8NC-



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titlePin Header J4
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titleVGA host socket information

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Schematic
Pin Header J4
Corresponding
SignalsConnected
toVGA_R0
to Notes
VGA_RED
J4 - 1...
3Bank 2Red channelVGA_GREENVGA_G0...3Bank 2Green channelVGA_BLUEVGA_B0...3Bank 2Blue channelVGA_RGB_HSYNCVGA_HSBank 2Horizontal syncVGA_RGB_VSYNCVGA_VSBank 2Vertical sync

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

6AIN0...5FPGA Bank 1 and ADC/DAC



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titlePin Header J5

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Pin Header J5SignalsConnected to Notes
J5 - 1I2C_SCLFPGA Bank 6 and EEPROM (U18, U20)Pulled-up to 3.3V.
J5 - 2I2C_SDAFPGA Bank 6 and EEPROM (U18, U20)Pulled-up to 3.3V.
J5 - 33.3V3.3 V
J5 - 4GNDGND


Micro USB 2.0 Connector

FTDI FT2232 (U14) can be accessed through micro USB 2.0 B connector (J10) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART or other standards.

RJ45 Connectors

TEI0009 is equipped with two RJ45 connectors and two Ethernet PHYs. RJ45 connectors J8 and J9 are connected to Ethernet PHYs U17 and U19 respectively.

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titleRJ45 Connectors Information
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Chip/Interface
Pin
Designator
Schematic
NotesQSPI Flash memoryU12SDRAM memoryU10PSRAM memoryU37 Segment LEDD11FTDI FT2232U14Ethernet PHYU17, U19Configuration DeviceU5AD/DAU2EEPROMU15, U18, U20User LEDsD2...D17OscillatorsU16, U22

QSPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

ETH1 PinETH2 PinNotes
TD+ETH1_TX_P, ETH2_TX_PU17 - TXPU19 - TXP
CTETH1_CTREF_TCT, ETH2_CTREF_TCT--
TD-ETH1_TX_N, ETH2_TX_NU17 - TXMU19 - TXM
RD+ETH1_RX_P, ETH2_RX_PU17 - RXPU19 - RXP
CTETH1_CTREF_RCT, ETH2_CTREF_RCT--
RD-ETH1_RX_N, ETH2_RX_NU17 - RXMU19 - RXM
LED GreenETH1_LED0, ETH2_LED0U17 - LED0/NWAYENU19 - LED0/NWAYEN
LED YellowETH1_LED1, ETH2_LED1U17 - LED1/SPEEDU19 - LED1/SPEED


D-Sub Connector

TEI0009 is equipped with a D-Sub connector which provides interface to Cyclone 10 LP through Bank 2.

F_IO0
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titleVGA Host Socket Information

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titleQuad SPI interface MIOs and pins

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Pin
Schematic
Schematic
Corresponding SignalsConnected
to 
toNotes
CS
VGA_RED
F_CS
VGA_R0...3Bank
7 
2
CLK
Red Channel
F
VGA_
CLK
Bank 7 IO0...3
GREENVGA_G0...3Bank
7