Versions Compared

Old Version 42

changes.mady.by.user ED

Saved on

compared with

New Version Current

changes.mady.by.user ED

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Scroll pdf ignore

Table of Contents

Table of Contents

Overview

The Cyclone10 Cyclone 10 LP Reference Kit is the world's first development board with a 55 kLE (Logic Elements) Intel Cyclone 10 LP and a variety of interfaces for numerous applications. The board is comprehensively tested and ready for use with end products and can also be ordered in customer-specific variants according to your requirements.

...

Page properties
hiddentrue
idComments

Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

  • Intel® Intel Cyclone 10 LP  LP [10CL055YU484C8G],
    • Package: UBGA-484
    • Speed Grade: 8 (Slowest)
    • Temperature: 0 °C to 85° C
    • Package compatible device 10CL016, 10CL040, 10CL055, 10CL080 as assembly variant on request is possible
  • 16 MBit (2 MByte) Flash Memory (optional up to 32 MBit (4 MByte) possible)
  • Integrated USB-JTAG Programmer
  • Pin Header Connectors
  • 64 MBit (8 MByte) SDRAM , (optional up to 512 MBit (64 MByte) memory mountable)
  • 64 MBit (8 MByte) User Quad-SPI Flash Memory , (optional up to 128 MBit (16 MByte) memory mountable)
  • 64 MBit (8 MByte) HyperRAM (Pseudo SRAM) , (optional up to 128 MBit (16 MByte)) memory mountable
  • 2x MAC Address EEPROM
  • 2x Fast Ethernet PHY (10/100 Mbps)
  • 8-Channel, 12-Bit, configurable ADC/DAC
  • D-Sub Connector
  • 2x RJ45 Connector
  • LEDs:
    • Status LEDs, Power LED
    • 13x User LEDs
    • 7-Segment Display
  • Push Buttons:
    • 2x Reset Push Buttons
    • 5x User Push Buttons
  • I/O: 70 GPIO
  • 5 V Power Supply
  • Dimension: 95 mm x 110 mm
  • Others:
    • Reverse Supply Protection
    • Undervoltage/Overvoltage Protection

...

Scroll Title
anchorFigure_OV_BD
titleTEI0009 block diagramBlock Diagram


Scroll Ignore
draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision1217
diagramNameTEI0009_OV_BD
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth637640


Scroll Only


Main Components

...

Scroll Title
anchorFigure_OV_BD
titleTEI0009 main componentsMain Components


Scroll Ignore
draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision7
diagramNameTEI0009_OV_MC
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth640


Scroll Only


  1. Power Jack, J12
  2. RJ45 Socket, J8...9
  3. D-Sub Connector, J11
  4. Push Button (Reset), S7
  5. Grove Connector, J5
  6. Undervoltage/Overvoltage Protector, U9
  7. 7-Segment LED, D11
  8. 1x6 Pin Header, J4
  9. 1x8 Pin Header, J2...3
  10. 8x User LEDs (Red), D2...9
  11. 5x User LEDs (Red), D13...17
  12. 5x User Push Buttons, S1 - S3...6
  13. Red LED (CONF_DONE), D10
  14. PSRAM Memory, U3
  15. SDRAM Memory, U10
  16. Voltage Regulator, U4 - U7
  17. AD/DA Converter, U2
  18. 6x Pmod Host Socket, P1...6
  19. Intel® Intel Cyclone 10 LP, U1
  20. Serial Configuration Memory, U5
  21. 1x10 Pin Header, J1
  22. EEEPROMEEPROM, U15 - U18 - U20
  23. FTDI USB2 USB 2 to JTAG/UART Converter, U14
  24. Micro USB 2.0, J10
  25. Push Button (RST_GPIO), S2
  26. Oscillator, U22
  27. Ethernet PHY, U17 - U19
  28. QSPI Flash Memory, U12

...

Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices Delivery State of Programmable Devices on the moduleModule

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Storage device name

Content

Notes

QSPI Flash (U12)

Not programmed


EEPROM (U15)Programmed

FTDI configurationConfiguration

EEPROM (U18, U20)Not programmedExcept Ethernet MAC
SDRAM (U10)Not programmed


PSRAM (U3)Not programmed
Serial Configuration Memory (U5)Programmed


...

Scroll Title
anchorTable_OV_BP
titleBoot process.Process

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

MODE Signal State

MSEL0MSEL1MSEL2MSEL3Connected to Boot Mode

MSEL[0:3]

0100Bank 6

AS (Active Serial)


...

Scroll Title
anchorTable_OV_RST
titleReset process.Process

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal

Connected to Note

RESET

S7 (Push button)S7, Push ButtonConnected to nCONFIG.


Signals, Interfaces and Pins

...

FPGA bank number and number of I/O signals connected to the B2B connectorconnectors:

Scroll Title
anchorTable_SIP_B2B
titleGeneral I/O to Pin header Header and Pmod SMD connectors informationConnectors Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

FPGA BankConnector I/O Signal CountVoltage LevelNotes
Bank 1J1 (Pin header)8 Single ended3.3 V
J2 (Pin header)8 Single ended3.3 V
J4 (Pin header)6 Single ended3.3 V
Bank 2

J3 (Pin header)

1 Single ended3.3 V
P1 (Pmod Host Socket)8 Single ended3.3 V
P2 (Pmod Host Socket)8 Single ended3.3 V
J11 (VGA host Host Socket)14 Single ended3.3 V
Bank 6J5 (Grove connectorConnector)2 Single ended3.3 V
Bank 7P5 (Pmod Host Socket)8 Single ended3.3 V
P6 (Pmod Host Socket)8 Single ended3.3 V
Bank 8P3 (Pmod Host Socket)8 Single ended3.3 V
P4 (Pmod Host Socket)8 Single ended3.3 V


...

Scroll Title
anchorTable_SIP_SMD
titlePMod SMD host socket informationPmod SMD Host Socket Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorSignalsConnected to Notes
P1P1_IO1...8Bank 2
P2P2_IO1...8Bank 2
P3P3_IO1...8Bank 8
P4P4_IO1...8Bank 8
P5P5_IO1...8Bank 7
P6P6_IO1...8Bank 7


...

Scroll Title
anchorTable_SIP_RJ45
titleRJ45 connectors informationConnectors Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

PinSchematicETH1 PinETH2 PinNotes
TD+ETH1_TX_P, ETH2_TX_PU17 - TXPU19 - TXP
CTETH1_CTREF_TCT, ETH2_CTREF_TCT--
TD-ETH1_TX_N, ETH2_TX_NU17 - TXMU19 - TXM
RD+ETH1_RX_P, ETH2_RX_PU17 - RXPU19 - RXP
CTETH1_CTREF_RCT, ETH2_CTREF_RCT--
RD-ETH1_RX_N, ETH2_RX_NU17 - RXMU19 - RXM
LED GreenETH1_LED0, ETH2_LED0U17 - LED0/NWAYENU19 - LED0/NWAYEN
LED YellowETH1_LED1, ETH2_LED1U17 - LED1/SPEEDU19 - LED1/SPEED


D-Sub

...

Connector

TEI0009 is equipped with a D-Sub connector which provides interface to Cyclone 10 LP through Bank 2.

Scroll Title
anchorTable_SIP_VGA
titleVGA host socket informationHost Socket Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SchematicCorresponding SignalsConnected toNotes
VGA_REDVGA_R0...3Bank 2Red channelChannel
VGA_GREENVGA_G0...3Bank 2Green channelGreen Channel
VGA_BLUEVGA_B0...3Bank 2Blue channelBlue Channel
VGA_RGB_HSYNCVGA_HSBank 2Horizontal syncSync
VGA_RGB_VSYNCVGA_VSBank 2Vertical syncSync


On-board Peripherals

Page properties
hiddentrue
idComments

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

...

Scroll Title
anchorTable_OBP
titleOn-board peripheralsPeripherals

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Chip/InterfaceDesignatorNotes
QSPI Flash memoryMemoryU12
SDRAM memoryMemoryU10
PSRAM memoryMemoryU3
7-Segment LEDD11
FTDI FT2232U14
Ethernet PHYU17, U19
Serial Configuration MemoryU5
ADC/DACU2
EEPROMU15, U18, U20
User LEDsD2...D10, D13...D17
Push ButtonsS1...7
OscillatorsU16, U22


...

Page properties
hiddentrue
idComments

Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

There is a 64MBit 64 MBit (8 MByte) QSPI Flash memory (U12) provided by Integrated Silicon Solution Inc. which can be used to store data or configuration. Up to 128 MBit (16 MByte) memory is possible available on other assembly option.

Scroll Title
anchorTable_OBP_SPI
titleQuad SPI interface Interface MIOs and pinsPins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

PinSchematicConnected to Notes
CSF_CSBank 7 
CLKF_CLKBank 7 
IO0...3F_IO0...3Bank 7 


...

The TEI0009 has 64 MBit (8 MByte) volatile memory provided by Integrated Silicon Solution Inc., SDRAM IC(U10) for storing user application code and data. Up to 512 MBit (64 MByte) SDRAM is possible available on other assembly option.

...

The TEI0009 is integrated with 64 Mbit (8 MByte) Pseudo Static Random Access Memory (PSRAM) using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation. Up to 128 MBit (16 MByte) memory is possible available on other assembly option.

  • Part number:  IS66WVH8M8BLLIS66WVH8M8

  • Supply voltage: 3.3 V

  • Clock Frequency: 100 MHz

  • Temperature: -40°C to 85°C (optional other ranges are available)

...

Scroll Title
anchorTable_OBP_7SEG
titleLED 7-Segment pinsLED Pins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

PinSchematicConnected to Notes
A/L1SEG_CABank 6 
B/L2SEG_CBBank 6 
C/L3SEG_CCBank 6
DSEG_CDBank 6
ESEG_CEBank 6
FSEG_CFBank 6
GSEG_CGBank 6
DPSEG_CDPBank 6
A1SEG_ANBank 6
A2SEG_AN4Bank 6
A3SEG_AN3Bank 6
A4SEG_AN2Bank 6
L1-L3SEG_AN1Bank 6


...

Scroll Title
anchorTable_OBP_FTDI
titleFTDI chip interfaces Chip Interfaces and pinsPins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

FTDI Chip PinSignal Schematic NameConnected toNotes
ADBUS0TCKBank 1JTAG interface
ADBUS1TDIBank 1
ADBUS2TDOBank 1
ADBUS3TMS

Bank 1

BDBUS0...7BDBUS0...7Bank 6
BCBUS0...7BCBUS0...7Bank 6
EECSEECSEEPROM, U15
EECLKEECLKEEPROM, U15
EEDATAEEDATAEEPROM, U15
OSCICK12M12 MHz Oscillator, U16
DMD_NMicro USB 2.0, J10
DPD_PMicro USB 2.0, J10


...

Scroll Title
anchorTable_OBP_EEPSCM
titleFTDI and EEPROM pin connectionsSerial Configuration Memory

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Configuration Memory PinSignal Schematic NameConnected toNotes
DATA1AS_DATA0U1, Bank 1

DATA0AS_ASDOU1, Bank 1
nCSAS_nCSU1, Bank 1
DCLKAS_DCLK

U1, Bank 1



...

Scroll Title
anchorTable_OBP_ETH
titleEthernet PHY connections Connections and pinsPins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Ethernet PHY PinSignal Schematic Names (ETH1/ETH2)ETH 1ETH 2Note
TXD0...3ETH1_TXD0...3, ETH2_TXD0...3Bank 5Bank 5
TXCETH1_TXC, ETH2_TXCBank 5Bank 5
TXENETH1_TXEN, ETH2_TXENBank 5Bank 5
RXD0...3ETH1_RXD0...3, ETH2_RXD0...3Bank 5Bank 5
RXC/B-CAST_OFFETH1_RXC, ETH2_RXCBank 5Bank 5
RXER/ISOETH1_RXER, ETH2_RXERBank 5Bank 5
INTRP/nNAND_TreeETH1_INTRP, ETH2_INTRPBank 5

Bank 5


XIETH1_CLKIN, ETH2_CLKINOscillator, U22Oscillator, U22
MDCETH1_MDC, ETH2_MDCBank 5Bank 5
MDIOETH1_MDIO, ETH2_MDIOBank 5Bank 5
COL/CONFIG0ETH1_COL, ETH2_COLBank 5Bank 5
CRS/CONFIG1ETH1_CRS, ETH2_CRSBank 5Bank 5
RXDV/CONFIG2ETH1_RXDV, ETH2_RXDVBank 5Bank 5
LED0/NWAYENETH1_LED0, ETH2_LED0

RJ45 - Green LED, J8

RJ45 - Green LED, J9


LED1/SPEEDETH1_LED1, ETH2_LED1

RJ45 - Yellow LED, J8

RJ45 - Yellow LED, J9


nRSTETH1_RST, ETH2_RSTBank 5Bank 5
RXMETH1_RX_N, ETH2_RX_NRJ45, J8RJ45, J9
RXPETH1_RX_P, ETH2_RX_PRJ45, J8RJ45, J9
TXMETH1_TX_N, ETH2_TX_NRJ45, J8RJ45, J9
TXPETH1_TX_P, ETH2_TX_PRJ45, J8RJ45, J9


...

Scroll Title
anchorTable_OBP_EEP
titleFTDI and EEPROM pin connectionsPin Connections

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorEEPROM PinSignal Schematic NamesConnected to Notes
U15CSEECSFTDI, U14
CLKEECLKFTDI, U14
DIN/DOUTEEDATAFTDI, U14


...

Scroll Title
anchorTable_OBP_EEP
titleI2C EEPROM interface Interface MIOs and pinsPins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorPinSchematicConnected to Grove HeaderNotes
U18, U20SCLI2C_SCLBank 6J5
SDAI2C_SDABank 6J5


...

Scroll Title
anchorTable_OBP_I2C_EEPROM
titleI2C address Address for EEPROM

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

I2C AddressDesignatorNotes
0x50U18
0x51U20


...

The TEI0009 module is equipped with a 12 bit -Bit ADC/DAC (U2).

Scroll Title
anchorTable_OBP_A2D
titleADC/DAC interface Interface and pinsPins

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

PinsSchematicConnected toNotes

nRESET

ADDA_RSTNBank 2, U1
nSYNCADDA_SYNCBank 2, U1
SCLKMCLKBank 2, U1
SDIMOSIBank 2, U1
SDOMISOBank 2, U1
VREFAREFPin Header, J1External reference is 1 V to 3.3 V.  → ???
Internal reference is 2.5 V.
IO0...5AIN0...5

Bank 1, U1

Pin Header, J4


IO6AIN6Testpoint, TP1
IO7AIN7Testpoint, TP2


LEDs

Scroll Title
anchorTable_OBP_LED
titleOn-board LEDs

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SchematicDesignator ColorConnected toActive LevelNote
LED1...8D2...9RedBank 3High
LED_PB1...5D13...17RedBank 7High
CONF_DONED10RedBank 6Low
3.3VD1Green3.3VHigh


Push Buttons

Scroll Title
anchorTable_OBP_PBTN
titleOn-board Push Buttons

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SchematicDesignator Connected toFunctionalityNote
RESETS7RESETBank 1HighReset
S2RST_GPIOS2HighBank 4Reset/GPIOS1, S3...6
USER_BTN1...5User push buttonsconnected to bank 3

Clock Sources

S3Bank 3User Push Button
USER_BTN2S4Bank 3User Push Button
USER_BTN3S5Bank 3User Push Button
USER_BTN4S6Bank 3User Push Button
USER_BTN5S1Bank 3User Push Button


Clock Sources

Scroll Title
anchorTable_OBP_CLK
titleOscillators
Scroll Title
anchorTable_OBP_CLK
titleOsillators

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DesignatorDescriptionFrequencyNote
U22MEMS Crystal Oscillator25 MHz
U16MEMS Crystal Oscillator12 MHz


Power and Power-On Sequence

...

Power supply with minimum current capability of 1A 3 A for system startup is recommended.

...

Scroll Title
anchorFigure_PWR_PD
titlePower Distribution


Scroll Ignore
draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision711
diagramNameTEI0009_PWR_PD
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth639540


Scroll Only


Power-On Sequence

There is no the following power-on sequence, After power on, all regulators will be enabled as you can see in the diagram below.. The DCDC converter U7 enables the device U4 according to the diagram below.

Scroll Title
anchorFigure_PWR_PS
titlePower Sequency


Scroll Ignore
draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision610
diagramNameTEI0009_PWR_PS
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth639538


Scroll Only


Voltage

...

Protection Circuit

There is a diod transient voltage suppression diode (D12) which protects the board from reverse polarity, Additionaly voltage spikes. Additionaly, there is an Over/under voltage (IC) which protects the board from over voltage damagesovervoltage / undervoltage protection device (U9) for board protection.

Scroll Title
anchorFigure_PWR_VMC
titleVoltage Monitor Protection Circuit


Scroll Ignore
draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision15
diagramNameTEI0009_PWR_VM
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth641509


Scroll Only

Image Modified


Power Rails

Scroll Title
anchorTable_PWR_PR
titleModule power rails.Power Rails

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
tableStylingconfluence
sortEnabledfalse
cellHighlightingtrue


Connector Designator
VCC /

VCCIO Schematic Name

Pin VCCDirectionNotes
J12VIN15 VIn
J33.3V2, 43.3 V Out
5V55 V Out
J53.3V33.3 V Out


Bank Voltages

Scroll Title
anchorTable_PWR_BV
titleZynq SoC bank voltages.Intel Cyclone 10 LP Bank Voltages

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Bank          

Schematic Name

Voltage

Notes
Bank 1VCCIO13.3VBank 2

VCCIO2

3.3VBank 3 VCCIO33.3V.8VCCIO1...8Bank 4VCCIO43.3VBank 5VCCIO53.3VBank 6VCCIO63.3VBank 7VCCIO73.3VBank 8VCCIO83.3V


Technical Specifications

Absolute Maximum Ratings

Scroll Title
anchorTable_TS_AMR
titleAbsolute maximum ratingsMaximum Ratings

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

SymbolsDescriptionMinMaxUnitNote
VIN 
Input supply voltage
Input Supply Voltage (J12)
4.5
-5.0
5.
0
5V
VCCIOI/O buffers power supply

AREFExternal Reference Voltage for ADC/DAC (J1 - 8)-0.
5
33.
75
6V
VCCINTCore voltage-0.51.8VVCCD_PLLPLL digital power supply-0.51.8VVCCAPhase-locked loop (PLL) analog power supply
Only for input usage.
AIN0...5Input Voltage for ADC/DAC (J4)-0.
5
33.
75
6V
V_ANAnalog Input Voltage on
Only for input usage.
AIN6...7Input Voltage for ADC/DAC (
U2
TP1...2)-0.33.6V
V_DIGDigital Input Voltage on ADC/DAC (U2
Only for input usage.
EXT_RSTExternal Reset (J3 - 3)-0.
3
5
3
4.
6
2V
V

D0_
REF_IN
RXD, D1_TXD, D2...7Arduino Interface (J2
Internal Reference Voltage Voltage on ADC/DAC (U2
)-0.
3
5
3
4.
6
2V
V_REF_EXExternal Reference Voltage Voltage on ADC/DAC (U2)-0.33.6V
Only for input usage.

D8...13, D14_SDA, D15_SCL

Arduino Interface (J1 - 1...6, 9...10)-0.54.2VOnly for input usage.
I2C_SCL, I2C_SDAI2C Interface (J5 - 1...2)-0.34.2VOnly for input usage.

P1_IO1...8, P2_IO1...8,

P3_IO1...8, P4_IO1...8,

P5_IO1...8, P6_IO1...8,

Pmod Interface (P1...6)-0.54.2VOnly for input usage.
CLK_INExternal FPGA Clock (J19)-0.54.2V
CLK_OUTClock / IO (J20)-0.54.2VOnly for input usage.
T_STGStorage Temperature-3585°CSee LTC2623WC datasheet


Recommended Operating Conditions

...

Scroll Title
anchorTable_TS_ROC
titleRecommended operating conditions.Operating Conditions

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

VCCIO1353.465See  AD5592RBCPZ datasheet.
ParameterMinMaxUnitsReference Document
VIN 4.755.25V

AREF13.3V

AIN0...50AREFVSee Cyclone 10 LP datasheet.
VCCINT1.151.25VSee Cyclone 10 LP datasheet.
VCCD_PLL1.151.25VSee Cyclone 10 LP datasheet.
VCCA2.3752.625VSee Cyclone 10 LP datasheet.
V_AN03.3VSee  AD5592RBCPZ datasheet.
V_DIG03.3VSee  AD5592RBCPZ datasheet.
V_REF_IN13VSee  AD5592RBCPZ datasheet.


AIN6...70AREFV

EXT_RST-0.53.6V

D0_RXD, D1_TXD, D2...7-0.53.6V

D8...13, D14_SDA, D15_SCL

-0.53.6V

I2C_SCL, I2C_SDA-0.33.3V

P1_IO1...8, P2_IO1...8,

P3_IO1...8, P4_IO1...8,

P5_IO1...8, P6_IO1...8,

-0.53.6V

CLK_IN-0.53.6V

CLK_OUT-0.53.6VV_REF_EX2.452.55V

T_OP070°C

See SDRAM W9864G6JT datasheet



...

Scroll Title
anchorFigure_TS_PD
titlePhysical Dimension


Scroll Ignore
draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision23
diagramNameTEI0009_TS_PD
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth640


Scroll Only
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue


...

Scroll Title
anchorTable_VCP_SO
titleTrenz Electronic Shop Overview

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Trenz shop TE0728 TEI0009 overview page
English pageGerman page


Revision History

Hardware Revision History

...

Scroll Title
anchorTable_RH_HRH
titleHardware Revision History

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateRevisionChangesDocument Link
2018-2-1901-
REV01
---
2018-7-1802
  • Change J5 from SMD
connector
  • Connector to GROVE
connectorConnect clock
  • Connector
  • Change connection of 12 MHz clock from Bank 1 to Bank
1
  • 6
Connect
  • Change connection of I2C
SLA/SDA
  • SDA/SCL from Bank 3 to Bank
3
  • 6
Remove
  • SMA Coaxial
straight
  • Connector J19, J20 not mounted
  • Change connection of CLK_IN/CLK_OUT from Bank 4 to Bank 8
  • Remove DIP Switch S1
  • Add 5
red
  • LEDs (Red)
  • Add 2 Push
buttons
  • Buttons
  • Add 64 Mbit QSPI
flash memory
  • Flash Memory
  • Change SDRAM
memory, 143 MHz to 166 MHz
  • Memory
  • Remove
10bit
  • 10-Bit ADC
  • Remove
10bit
  • 10-Bit DAC
  • Add
12bit DAC/ADC
  • Remove SMA Coaxial straight J19,J20
  • Remove SMA Coaxial straight J19,J20
  • Remove Tranciever USB
  • Remove DIP switch S2
  • Different Power Dependencies
  • Remove 24MHz Oscillator
    • 12-Bit ADC/DAC
    • Remove USB Transceiver
    • Remove 24 MHz Oscillator
    • Remove DIP Switch S2
    • Changed Power Supply Circuit
    • Add 4 Pmod Host Sockets
    Add 4x Pmod SMD host socket
    		REV02


    Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

    Scroll Title
    anchorFigure_RV_HRN
    titleBoard hardware revision number.Hardware Revision Number


    Scroll Ignore
    draw.io Diagram
    borderfalse
    viewerToolbartrue
    fitWindowfalse
    diagramDisplayName
    lboxtrue
    revision2
    diagramNameTEI0009_RV_HRN
    simpleViewerfalse
    width
    linksauto
    tbstylehidden
    diagramWidth196


    Scroll Only


    ...

    Scroll Title
    anchorTable_RH_DCH
    titleDocument change history.Change History

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    change list
    DateRevisionContributorDescription

    Page info
    infoTypeModified date
    dateFormatyyyy-MM-dd
    typeFlat

    Page info
    infoTypeCurrent version
    prefixv.
    typeFlat
    showVersionsfalse

    Page info
    infoTypeModified by
    typeFlat
    showVersionsfalse

    • Updated

    		v.40Pedram Babakhani
    • initial release

    --

    all

    Page info
    infoTypeModified users
    typeFlat
    showVersionsfalse

    • --


    ...