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Scroll Title |
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anchor | Table_OBP |
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title | On-board Peripherals |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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QSPI Flash Memory
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The TEI0009 is integrated with 64 Mbit (8 MByte) Pseudo Static Random Access Memory (PSRAM) using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation. Up to 128 MBit (16 MByte) memory is available on other assembly option.
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Scroll Title |
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anchor | Table_PWR_PR |
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title | Module Power Rails |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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tableStyling | confluence |
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sortEnabled | false |
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cellHighlighting | true |
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Connector Designator | VCCIO Schematic Name | Pin | VCC | Direction | Notes |
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J12 | VIN | 1 | 5 V | In |
| J3 | 3.3V | 2, 4 | 3.3 V | Out |
| 5V | 5 | 5 V | Out |
| J5 | 3.3V | 3 | 3.3 V | Out |
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Bank Voltages
Scroll Title |
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anchor | Table_PWR_BV |
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title | Intel Cyclone 10 LP Bank Voltages |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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| Schematic Name | | Notes |
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Bank 1...8 | VCCIO1...8 | 3.3V |
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