Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.


Page properties
hiddentrue
idComments

Template Revision 2.6 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"


HTML
<!--
Template Revision 1.2
Basic Notes
 - export PDF to download, if vivado revision is changed!
 - Template is for different design and SDSoC and examples, remove unused or wrong description!
 -->
Scroll Only (inline)
Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
Scroll pdf ignore

Table of contents

Table of Contents
outlinetrue

Overview

HTML
<!--
General Design description
 -->

Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.

Key Features

HTML
<!--
Add Basic Key Features of the design (should be tested)
 -->
Excerpt
  • QSPI
  • SDK
  • Custom Carrier (minimum PS Design with available module components only)
  • Special FSBL for QSPI Programming

Revision History

HTML
<!--
- Add changes from design
- Export PDF to download, if vivado revision is changed!
  -->

...

  • additional notes for FSBL generated with Win SDK
  • changed *.bif

...

  • new assembly variant

...

  • Update Board Part for TEBF0808
    • no changes for test board design and minimal board parts

...

  • rework Board Part Files

...

TE0808-test_board-vivado_2017.2-build_07_20171220192501.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_07_20171220192448.zip

...

  • Update Board Part Files

...

  • Update Board Part CSV File
  • Regenerate design
tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>


Page properties
hiddentrue
idComments

Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



  • ...


Scroll pdf ignore

Table of contents

Table of Contents
outlinetrue

Overview

Page properties
hiddentrue
idComments

Notes :

Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

Page properties
hiddentrue
idComments

Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vivado 2018.3
  • QSPI
  • SDK
  • Custom Carrier (minimum PS Design with available module components only)
  • Modified FSBL (some additional outputs only)
  • Special FSBL for QSPI Programming

Revision History

Page properties
hiddentrue
idComments

Notes :

  • add every update file on the download
  • add design changes on description


Scroll Title
anchorTable_DRH
titleDesign Revision History

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateVivadoProject BuiltAuthorsDescription
2019-05-062018.3

...

TE0808-test_board_noprebuilt-vivado_

...

2018.

...

3-build_05_

...

20190507124141.zip
TE0808-test_board-vivado_2018.3-build_05_20190507124130.zip
John Hartfiel

...

  • Update Board Part CSV File with new Flash assembly variants
  • custom FSBL
2018-07-112018

...

.2TE0808-test_board_noprebuilt-vivado_

...

2018.2-build_

...

02_

...

20180711143743.zip
TE0808-test_board

...

-vivado_

...

2018.2-build_

...

02_

...

20180711143702.zipJohn Hartfiel

...

  • initial release

Release Notes and Know Issues

HTML
<!--
- add known Design issues and general Notes for the current revision
 -->

...

Requirements

Software

HTML
<!--
Add needed external Software
   -->

...

Hardware

HTML
<!--
Hardware Support
   -->

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

Xilinx has stopped ES1 support with 2018.2, please use 2017.4 reference design

...

Note: Design contains also Board Part Files for TE0808+TEBF0808 configuration, this boart part files are not used for this reference design.

Design supports following carriers:

...

Additional HW Requirements:

...

Content

HTML
<!--
Remove unused content
  -->

For general structure and of the reference design, see Project Delivery

Design Sources

...

  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-03-292017.4TE0808-test_board-vivado_2017.4-build_07_20180329151341.zip
TE0808-test_board_noprebuilt-vivado_2017.4-build_07_20180329151355.zip
John Hartfiel
  • new assembly variant
2018-01-162017.4TE0808-test_board-vivado_2017.4-build_04_20180116144644.zip
TE0808-test_board_noprebuilt-vivado_2017.4-build_04_20180116144657.zip
John Hartfiel
  • Update Board Part for TEBF0808
    • no changes for test board design and minimal board parts
2018-01-152017.4TE0808-test_board-vivado_2017.4-build_03_20180115084954.zip
TE0808-test_board_noprebuilt-vivado_2017.4-build_03_20180115085020.zip
John Hartfiel
  • rework Board Part Files
2017-12-202017.2

TE0808-test_board-vivado_2017.2-build_07_20171220192501.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_07_20171220192448.zip

John Hartfiel
  • Update Board Part Files
2017-11-222017.2TE0808-test_board-vivado_2017.2-build_05_20171122080211.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171122080228.zip
John Hartfiel
  • Update Board Part CSV File
  • Regenerate design
2017-11-162017.2

TE0808-test_board-vivado_2017.2-build_05_20171116151545.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171116151600.zip

John Hartfiel
  • Update Board Part CSV File with new Flash assembly variants
2017-11-132017.2TE0808-test_board-vivado_2017.2-build_05_20171113140954.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171113141908.zip
John Hartfiel
  • initial release


Release Notes and Know Issues

Page properties
hiddentrue
idComments
Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed


IssuesDescriptionWorkaroundTo be fixed version
No known issues---------

Requirements

Software

Page properties
hiddentrue
idComments

Notes :

  • list of software which was used to generate the design


SoftwareVersionNote
Vivado2018.3needed
SDK2018.3needed

Hardware

Page properties
hiddentrue
idComments

Notes :

  • list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Scroll Title
anchorTable_HWM
titleHardware Modules

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0808-ES1          es1_2gb      REV03|REV02 2GB      64MB       NA         NA               Not longer supported by vivado       
TE0808-ES2          es2_2gb      REV04|REV03 2GB      64MB       NA         NA               Slower DDR Speed                     
TE0808-2ES2         2es2_2gb     REV04|REV03 2GB      64MB       NA         NA               Slower DDR Speed                     
TE0808-04-09EG-1EA  9eg_1e_2gb   REV04       2GB      64MB       NA         NA               NA                                     
TE0808-04-09EG-1EB  9eg_1e_4gb   REV04       4GB      64MB       NA         NA               NA                                     
TE0808-04-09EG-1ED  9eg_1e_4gb   REV04       4GB      64MB       NA         1 mm connectorsNA                                     
TE0808-04-09EG-2IB  9eg_2i_4gb   REV04       4GB      64MB       NA         NA               NA                                     
TE0808-04-15EG-1EB  15eg_1e_4gb  REV04       4GB      64MB       NA         NA               NA                                     
TE0808-04-09EG-1EE  9eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-09EG-1EL  9eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     
TE0808-04-09EG-2IE  9eg_2i_4gb   REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-15EG-1EE  15eg_1e_4gb  REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-06EG-1EE  6eg_1e_4gb   REV04       4GB      128MB      NA         NA               NA                                     
TE0808-04-06EG-1E3  6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectorsNA                                     


Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this boart part files are not used for this reference design.


Design supports following carriers:

Scroll Title
anchorTable_HWC
titleHardware Carrier

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Carrier ModelNotes
Custom PCB use simple Board Part files, if MIO connected is different to TEBF0808
TEBF0808Used as reference carrier.
TEBT0808-01Change UART0 to UART1 (MIO68...69) and regenerate design



Additional HW Requirements:

Scroll Title
anchorTable_AHW
titleAdditional Hardware

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Additional HardwareNotes
------


Content

Page properties
hiddentrue
idComments

Notes :

  • content of the zip file

For general structure and of the reference design, see Project Delivery

Design Sources

Scroll Title
anchorTable_DS
titleDesign sources

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI


Additional Sources

Scroll Title
anchorTable_ADS
titleAdditional design sources

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

TypeLocationNotes
---------


Prebuilt

Page properties
hiddentrue
idComments

Notes :

  • prebuilt files
  • Template Table:

    • Scroll Title
      anchorTable_PF
      titlePrebuilt files

      Scroll Table Layout
      orientationportrait
      sortDirectionASC
      repeatTableHeadersdefault
      style
      widths
      sortByColumn1
      sortEnabledfalse
      cellHighlightingtrue

      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




Scroll Title
anchorTable_PF
titlePrebuilt files (only on ZIP with prebult content)

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Page properties
hiddentrue
idComments

Reference Design is available on:

Design Flow

Page properties
hiddentrue
idComments
Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Added
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. S(optional for manual changes)elect correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
      Important: Use Board Part Files, which did not ends with *_tebf0808
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects


Launch

Page properties
hiddentrue
idComments

Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0808
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP


SD

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with SDK Debugger into device, see:

Usage

QSPI Boot:

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select QSPI Card as Boot Mode
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from QSPI into OCM, 2. FSBL loads Application into DDR

Debugging:

System Design - Vivado

Page properties
hiddentrue
idComments

Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

Scroll Title
anchorFigure_BD
titleBlock Design
Image Added


PS Interfaces

Page properties
hiddentrue
idComments

Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

Scroll Title
anchorTable_PSI
titlePS Interfaces

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

TypeNote
DDR
QSPIMIO
UART0MIO, please select other one, if you have connected uart to second controller or other MIO
SWDT0..1
TTC0..3


Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - SDK/HSI

Page properties
hiddentrue
idComments
Note:
  • optional chapter separate

  • sections for different apps

For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

zynqmp_fsbl

TE modified 2018.3 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

zynqmp_fsbl_flash

TE modified 2018.3 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

hello_te0808

Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

Additional Software

Page properties
hiddentrue
idComments
Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

Page properties
hiddentrue
idComments
  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


Scroll Title
anchorTable_dch
titleDocument change history.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths2*,*,3*,4*
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Additional Sources

...

Prebuilt

HTML
<!-- 

<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
</table>
-->

...

File

...

File-Extension

...

Description

...

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

HTML
<!--
Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit
  -->

Reference Design is available on:

Design Flow

HTML
<!--
Basic Design Steps
Add/ Remove project specific 
  -->
Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Removed
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
                Important: Use Board Part Files, which did not ends with *_tebf0808
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

HTML
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->
Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

HTML
<!--
Example:
Connect JTAG and power on PCB
(if not done) Select 
correct device and Xilinx install path on "design_basic_settings.cmd" 
and create Vivado project with "vivado_create_project_guimode.cmd" or 
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

   -->
  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0808
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP

SD

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with SDK Debugger into device, see:

Usage

QSPI Boot:

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select QSPI Card as Boot Mode
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from QSPI into OCM, 2. FSBL loads application into DDR

Debugging:

System Design - Vivado

HTML
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
  -->

Block Design

Image Removed

PS Interfaces

Activated interfaces:

...

Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - SDK/HSI

HTML
<!--
optional chapter
separate sections for different apps
  -->

For SDK project creation, follow instructions from:

SDK Projects

Application

zynqmp_fsbl

Xilinx default FSBL

zynqmp_fsbl_flash

TE modified 2018.2 FSBL

Changes:

  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

hello_te0808

Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

Additional Software

HTML
<!--
Add Description for other Software, for example SI CLK Builder ...
 -->

No additional software is needed.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

HTML
<!-- Generate new entry: 1:add new row below first 2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview 3.Update Metadate =Page Information Macro Preview+1   -->

DateDocument Revision

Authors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info

...

infoTypeModified by
typeFlat

  • Release 2018.3
2018-07-11v.21John Hartfiel

...

  • Release 2018.2

2018-03-29

...

v.20John Hartfiel
  • new assembly variant
2018-02-08v.19John Hartfiel
  • Release 2017.4
2017-12-20v.14John Hartfiel
  • Design Update
  • typo correction on documentation
2017-11-22v.10John Hartfiel
  • Update assembly versions with new Flash size
  • Udate HW Table Name
  • Update Design
2017-11-14v.6John Hartfiel
  • Release 2017.2

...

--all

Page info

...

infoTypeModified users
dateFormatyyyy-MM-dd
typeFlat

--

...


Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices

...