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Scroll Title
anchorFigure_OV_BD
titleTExxxx TEI0009 main components


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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

Quad SPI Flash



EEPROM


DDR3 SDRAM


FTDI System Controller CPLD

PSDRAM

Config Device


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Scroll Title
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titleGeneral PL I/O to B2B connectors information

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2
FPGA BankConnectorConnector I/O Signal CountVoltage LevelNotes
Bank 1J1 (Pin header)8 Single ended3.3 V
J2 (Pin header)8 Single ended3.3 VJ4
J4 (Pin header)6 Single ended3.3 V
Bank 2J3

J3 (Pin header)

1 Single ended3.3 VBank 6J5
P1 (PMod SMD host socket)8 Single ended3.3 V

MIO Pins


P2 (PMod SMD host socket)8 Single ended3.3 V
J11 (VGA host Socket)14 Single ended3.3 V
Bank 6J5 (Grove connector)2 Single ended3.3 V
Bank 7P5 (PMod SMD host socket)8 Single ended3.3 V
P6 (PMod SMD host socket)8 Single ended3.3 V
Bank 8P3 (PMod SMD host socket)8 Single ended3.3 V
P4 (PMod SMD host socket)8 Single ended3.3 V


PMod SMD Host Socket

TEI0009 has 6 PMod 2x6 SMD Host Socket 90° which are connected to Cyclon 10 LP.

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titlePMod SMD host socket information

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DesignatorSignalsConnected to Notes
P1P1_IO1...8Bank 2
P2P2_IO1...8Bank 2
P3P3_IO1...8Bank 8
P4P4_IO1...8Bank 8
P5P5_IO1...8Bank 7
P6P6_IO1...8Bank 7


UART Interface

UART access to TEI0009 is available on 1x8 pin header J2. 

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titleUART interface information

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SchematicPin HeaderConnected to Voltage LevelNotes
TXDJ2Bank 13.3 V
RXDJ2Bank 13.3 V


Micro USB2.0 Connector

U14(FTDI FT2232) can be accessed through Micro USB2.0 B Receptacle 90 (J10).

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titleMicro USB2.0 B Receptacle 90 ° information

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SchematicConnected to Voltage LevelNotes
USB_VBUSGND

D-U14 (FTDI FT2232)3.3 V
D+U14 (FTDI FT2232)3.3 V


RJ45 Connectors

TEI0009 is equipped with two RJ45 connectors and two Ethernet PHYs. RJ45 connectors J8 and J9 are connected to Ethernet PHYs U17 and U19 respectively. .

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titleRJ45 connectors information

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PinSchematicETH1 PinETH2 PinNotes
TD+ETH_TX_PU17- TXPU19- TXP
CTETH_CTREF_TCT--Connected to GND
TD-ETH_TX_NU17- TXMU19- TXM
RD+ETH_RX_PU17- RXPU19- RXP
CTETH_CTREF_RCT--Connected to GND
RD-ETH_RX_NU17- RXMU19- RXM
LED GreenETH_LED0U17- NWAYENU19- NWAYEN
LED YellowETH_LED1U17- SPEEDU19- SPEED


VGA socket Connectors

VGA host socket is connected to Cyclone 10 LP through Bank 2.

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

Notes
Scroll Title
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titleVGA host socket information

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SchematicCorresponding SignalsConnected toNotes
VGA_REDVGA_R0...3Bank 2Red channel
VGA_GREENVGA_G0...3Bank 2Green channel
VGA_BLUEVGA_B0...3Bank 2Blue channel
VGA_RGB_HSYNCVGA_HSBank 2Horizontal sync
VGA_RGB_VSYNCVGA_VSBank 2Vertical sync
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MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI
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titleMIOs pins
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MIO PinConnected toB2B


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

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Scroll Title
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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
SPI Flash memoryU12
SDRAM memoryU10
PSDRAM memoryU3
7 Segment D11
FTDI FT2232U14
Ethernet PHYU17, U19
Configuration DeviceU5
AD/DA ConverterU2
EEPROMU15, U18, U20
User LEDsD2...D17
OscillatorsU16, U22


Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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