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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | Connector | I/O Signal Count | Voltage Level | Notes |
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| Bank 1 | J1 (Pin header) | 8 Single ended | 3.3 V |
| | J2 (Pin header) | 8 Single ended | 3.3 V |
| | J4 (Pin header) | 6 Single ended | 3.3 V |
| | Bank 2 | J3 (Pin header) | 1 Single ended | 3.3 V |
| | P1 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| | P2 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| | J11 (VGA host Socket) | 14 Single ended | 3.3 V |
| | Bank 6 | J5 (Grove connector) | 2 Single ended | 3.3 V |
| | Bank 7 | P5 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| | P6 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| | Bank 8 | P3 (PMod SMD host socket) | 8 Single ended | 3.3 V |
| | P4 (PMod SMD host socket) | 8 Single ended | 3.3 V |
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PMod SMD Host Socket
TEI0009 has 6 PMod 2x6 SMD Host Socket 90° which are connected to Cyclon 10 LP.
| Scroll Title |
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| anchor | Table_SIP_SMD |
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| title | PMod SMD host socket information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Signals | Connected to | Notes |
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| P1 | P1_IO1...8 | Bank 2 |
| | P2 | P2_IO1...8 | Bank 2 |
| | P3 | P3_IO1...8 | Bank 8 |
| | P4 | P4_IO1...8 | Bank 8 |
| | P5 | P5_IO1...8 | Bank 7 |
| | P6 | P6_IO1...8 | Bank 7 |
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UART Interface
UART access to TEI0009 is available on 1x8 pin header J2.
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Chip/Interface | Designator | Notes |
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| SPI Flash memory | U12 |
| | SDRAM memory | U10 |
| | PSDRAM memory | U3 |
| | 7 Segment | D11 |
| | FTDI FT2232 | U14 |
| | Ethernet PHY | U17, U19 |
| | Configuration Device | U5 |
| | AD/DA Converter | U2 |
| | EEPROM | U15, U18, U20 |
| | User LEDs | D2...D17 |
| | Oscillators | U16, U22 |
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SPI Flash Memory
| Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| anchor | Table_OBP_RTC |
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| title | I2C interface MIOs and pins |
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| CS | F_CS | Bank 7 |
| | CLK | F_CLK | Bank 7 |
| | IO0...3 | F_IO0...3 | Bank 7 |
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SDRAM Memory
| Page properties |
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0009 has 64 Mb volatile , SDRAM IC(U10) for storing user application code and data.
Part number: W9864G6JT-6-ND
Supply voltage: 3.3 V
- Clock Frequency: 166MHz
Temperature: 0°C ~ 70°C
RTC
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| Scroll Title |
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| anchor | Table_OBP_I2C_RTC |
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| title | I2C interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U? Pin | Notes |
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| Scroll Title |
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| anchor | Table_OBP_I2C_RTC |
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| title | I2C Address for RTC |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | I2C Address | Designator | Notes |
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| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Color | Connected to | Active Level | Note |
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DDR3 SDRAM
| Page properties |
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.
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Ethernet
| Scroll Title |
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Zynq SoC connections |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Bank | Signal Name | ETH1 | ETH2 | Signal Description |
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