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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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SPI Flash |
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| | EEPROM |
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| | DDR3 SDRAM |
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| | FTDI System Controller CPLD |
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| | PSDRAMPSRAM |
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| | Config Device |
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Configuration Signals
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Chip/Interface | Designator | Notes |
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| SPI Flash memory | U12 |
| | SDRAM memory | U10 |
| | PSDRAM PSRAM memory | U3 |
| | 7 Segment | D11 |
| | FTDI FT2232 | U14 |
| | Ethernet PHY | U17, U19 |
| | Configuration Device | U5 |
| | AD/DA Converter | U2 |
| | EEPROM | U15, U18, U20 |
| | User LEDs | D2...D17 |
| | Oscillators | U16, U22 |
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The TEI0009 has 64 Mb volatile , SDRAM IC(U10) for storing user application code and data. Up to 512 MBit SDRAM is possibleon other assembly option.
Part number: W9864G6JT-6-ND
Supply voltage: 3.3 V
- Clock Frequency: 166MHz
Temperature: 0°C ~ 70°C
PSRAM Memory
The TEI0009 is integrated with 64Mbit Pseudo Static Random Access Memory (SDRAM) using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation.
Part number: IS66WVH8M8BLL
Supply voltage: 3.3 V
- Clock Frequency: 100MHz
Temperature: -40°C ~ 85°C
LED 7 Segment 4 Digit
the TEI0009 has a LED 7 Segment 4 Digit which is connected to Bank 6.
| Scroll Title |
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| anchor | Table_OBP_7SEG |
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| title | LED 7 Segment pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pin | Schematic | Connected to | Notes |
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| A/L1 | SEG_CA | Bank 6 |
| | B/L2 | SEG_CB | Bank 6 |
| | C/L3 | SEG_CC | Bank 6 |
| | D | SEG_CD | Bank 6 |
| | E | SEG_CE | Bank 6 |
| | F | SEG_CF | Bank 6 |
| | G | SEG_CG | Bank 6 |
| | DP | SEG_CDP | Bank 6 |
| | A1 | SEG_AN | Bank 6 |
| | A2 | SEG_AN4 | Bank 6 |
| | A3 | SEG_AN3 | Bank 6 |
| | A4 | SEG_AN2 | Bank 6 |
| | L1-L3 | SEG_AN1 | Bank 6 |
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FTDI FT2232H
The FTDI chip U14 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U15.
| Scroll Title |
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| anchor | Table_OBP_FTDI |
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| title | FTDI chip interfaces and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FTDI Chip Pin | Signal Schematic Name | Connected to | Notes |
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| ADBUS0 | TCK | Bank 1 | JTAG interface | | ADBUS1 | TDI | Bank 1 | | ADBUS2 | TDO | Bank 1 | | ADBUS3 | TMS | Bank 1 | | BDBUS0 | BDBUS0 | Bank 6 |
| | BDBUS1 | BDBUS1 | Bank 6 |
| | BDBUS2 | BDBUS2 | Bank 6 |
| | BDBUS3 | BDBUS3 | Bank 6 |
| | BDBUS4 | BDBUS4 | Bank 6 |
| | BDBUS5 | BDBUS5 | Bank 6 |
| | EECS | EECS | U15 (EEPROM) |
| | EECLK | EECLK | U15 (EEPROM) |
| | EEDATA | EEDATA | U15 (EEPROM) |
| | OSCI | CK12M | U16 (12MHz Oscillator) |
| | DM | D_N | J10 (Micro USB2.0) |
| | DP | D_P | J10 (Micro USB2.0) |
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Ethernet PHY
The TEI0009 is equipped with two Ethernet PHY (U19, U17) which are connected to two RJ45 connectors.
| Scroll Title |
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY connections and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Ethernet Pin | Signals | ETH 1 | ETH 2 | Note |
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| TXD0...3 | ETH_TXD0...3 | Bank 5 | Bank 5 |
| | TXC | ETH_TXC | Bank 5 | Bank 5 |
| | TXEN | ETH_TXEN | Bank 5 | Bank 5 |
| | RXD0...3 | ETH_RXD0...3 | Bank 5 | Bank 5 |
| | RXC//B-CAST_OFF | ETH_RXC | Bank 5 | Bank 5 |
| | RXER/ISO | ETH_RXER | Bank 5 | Bank 5 |
| | INTRP//NAND_Tree | ETH_INTRP | Bank 5 | Bank 5 |
| | XI | ETH_CLKIN | U22 (Oscillator) | Bank 5 |
| | MDC | ETH_MDC | Bank 5 | Bank 5 |
| | MDIO | ETH_MDIO | Bank 5 | Bank 5 |
| | COL/CONFIG0 | ETH_COL | Bank 5 | Bank 5 |
| | CRS/CONFIG1 | ETH_CRS | Bank 5 | Bank 5 |
| | RXDV/CONFIG2 | ETH_RXDV | Bank 5 | Bank 5 |
| | NWAYEN | ETH_LED0 | Bank 5 J8B (RJ45- Green LED) | Bank 5 J9B (RJ45-Green LED) |
| | SPEED | ETH_LED1 | Bank 5 J8C (RJ45-Yellow LED) | Bank 5 J9B (RJ45-Yellow LED) |
| | nRST | ETH_RST | Bank 5 | Bank 5 |
| | RXM | ETH_RX_N | J8 (RJ45) | J9 (RJ45) |
| | RXP | ETH_RX_P | J8 (RJ45) | J9 (RJ45) |
| | TXM | ETH_TX_N | J8 (RJ45) | J9 (RJ45) |
| | TXP | ETH_TX_P | J8 (RJ45) | J9 (RJ45) |
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RTC
| Scroll Title |
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| anchor | Table_OBP_RTC |
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| title | I2C interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U? Pin | Notes |
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