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On-board Peripherals

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hidden true id Comments
Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchor	Table_OBP
title	On board peripherals

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SDRAM

TEI0016 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

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hidden true id Comments
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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anchor	Table_OBP_SDRAM
title	SDRAM interface IOs and pins

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Signal Schematic Name

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A0 ... A13

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BA0 / BA1

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bank 3

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DQ0 ... DQ15

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bank 6

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DQM0 ... DQM1

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bank 6

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CS

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bank 3

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CKE

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bank 3

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RAS

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bank 3

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Row Address Strobe

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CAS

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bank 3

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Column Address Strobe

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FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

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anchor	Table_OBP_FTDI
title	FTDI chip interfaces and pins

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FPGA bank 1B, pin G1

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VBUS USB_VBUS It is connected to GND D+ FTDI U3, DP pin D- FTDI U3, DM pin

JTAG Interface

JTAG access to the TEI0016 SoM through pin header connector J4.

Scroll Title
anchor Table_SIP_JTG title JTAG pins connection
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true JTAG Signal Pin Header Connector Note TMS J4-6 TDI J4-5 TDO J4-4 TCK J4-3 JTAG_EN J4-2

On-board Peripherals

Page properties
hidden true id Comments
Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

Page properties
hidden true id Comments
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Scroll Title
anchor Table_OBP title On board peripherals
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Chip/Interface Designator Notes SDRAM U2 FTDI FT2232H U3 JTAG/UART Adapter SPI Flash Memory U5 EEPROM U9 Oscillator U7 12MHz clock source ADC U6 Analog to Digital Convertor 8x User LEDs D2...9 Red LEDs

SDRAM

TEI0016 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency.

Page properties
hidden true id Comments
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

Scroll Title
anchor Table_OBP_SDRAM title SDRAM interface IOs and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true SDRAM I/O Signals Signal Schematic Name Connected to Notes Address inputs A0 ... A13 bank 3 - Bank address inputs BA0 / BA1 bank 3 - Data input/output DQ0 ... DQ15 bank 6 - Data mask DQM0 ... DQM1 bank 6 - Clock CLK bank 3 Control Signals CS bank 3 Chip select CKE bank 3 Clock enable RAS bank 3 Row Address Strobe CAS bank 3 Column Address Strobe WE bank 3 Write Enable

FTDI FT2232H

The FTDI chip U3 converts signals from USB2 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9

SPI Flash Memory

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

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anchor Table_OBP_QSPIFTDI title Quad SPI Flash memory interfaceFTDI chip interfaces and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true FTDI Chip U3 Pin Signal Schematic Name Connected to Notes F_CS FPGA bank 8, pin B3 chip select Connected to Notes ADBUS0 TCK FPGA bank 1B, pin G2 JTAG interface ADBUS1 TDI FPGA bank 1B, pin F5 ADBUS2 TDO FPGA bank 1B, pin F6 ADBUS3 TMS FPGA bank 1B, pin G1 BDBUS0 BDBUS0F_CLK FPGA bank 8, pin A3 clock A4 user configurable BDBUS1 BDBUS1F_DI FPGA bank 8, pin A2 data in / out B4 user configurable BDBUS2 BDBUS2nSTATUS FPGA bank 8, pin C4 data in / out, configuration dual-purpose pin of FPGA B5 user configurable BDBUS3 BDBUS3DEVCLRN FPGA bank 8, pin B9 data in / out, configuration dual-purpose pin of FPGA A6 user configurable BDBUS4 BDBUS4 FPGA bank 8, pin B6 user configurable BDBUS5 BDBUS5F_DO FPGA bank 8, pin B2 data in / out

EEPROM

A7 user configurable

SPI Flash Memory

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interfaceThe configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

Scroll Title
anchor Table_OBP_EEPQSPI title I2C EEPROM interface MIOs and pinsQuad SPI Flash memory interface
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Signal Schematic Connected to Notes EECS FTDI U3, Pin EECS EECLK FTDI U3, Pin EECLK EEDATA FTDI U3, Pin EEDATA

A2D Convertor

Name Connected to Notes F_CS FPGA bank 8, pin B3 chip select F_CLK FPGA bank 8, pin A3 clock F_DI FPGA bank 8, pin A2 data in / out nSTATUS FPGA bank 8, pin C4 data in / out, configuration dual-purpose pin of FPGA DEVCLRN FPGA bank 8, pin B9 data in / out, configuration dual-purpose pin of FPGA F_DO FPGA bank 8, pin B2 data in / out

EEPROM

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9The TEI0016 board is equipped with the Analog Devices ADAQ7988BCCZ, 16-bit A2D converter (ADC).

Scroll Title
anchor Table_OBP_A2DEEP title A2D converter I2C EEPROM interface MIOs and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true PinsSchematic Connected to Notes IN+EECS U8FTDI U3, VOUT VREF_ADC IN- U12, VOUT SDI Bank 2, ADC_SDI SDO Bank 2, ADC_SDO SCK Bank 2, ADC_SCK CNV Bank 2, ADC_CNV

LEDs

Pin EECS EECLK FTDI U3, Pin EECLK EEDATA FTDI U3, Pin EEDATA

ADC

The TEI0016 board is equipped with the Analog Devices ADAQ7988BCCZ, 16-bit 500kSPS ADC.

Color

Scroll Title
anchor Table_OBP_LEDA2D title On-board LEDsA2D converter interface and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true	Designator

Pins	Connected to

Active Level

Notes

NoteD2...9RedLED1...8Active HighUser LEDsD10RedCONF_DONEActive LowConfiguration DONE LEDD1Green3.3V Power RailActive HighAfter power on it will be on