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Note: 'Key Features' description: Important components and connector or other Features of the module → please sort and indicate assembly options |
- Intel Intel® Cyclone 10 LP FPGA LP [10CL055YU484C8G, 55 kLE in 484-pin],
- Package: UBGA-484
- Speed Grade: 8 (Slowest)
- Temperature: 0°C ~ 85°C
- Package compatible device 10CL016, 10CL040, 10CL080 as assembly variant on request is possible
- 16 MBit flash memory (optional up to 32 MBit possible)
- Integrated USB USB2.0 Programmer 2
- ConnectorsPin Header connectors
- 256 MBit (optional up to 512 MBit possible) SDRAM
- 128 MBit (optional up to 512 MBit possible) User Quad-SPI Flash memory
- 64 MBit HyperRAM(Pseudo SRAM) (optional up to 128 MBit possible)
- FTDI - System Controller (CPLD)
- 2 x 2x MAC address EEPROM
- 2 x 2x Fast Ethernet PHY (10/100 Mbps)
- 8-channel, 12-bit, configurable ADC /DAC with on-chip reference
- D-Sub connector
- 2x RJ45 connector
- LEDs:
- Status LEDs, Power LED
- 13 x 13x User LEDs
- 1 x 7-segment display
- 2 x reset buttons
- Push bottuns:
- 2x Reset Push buttons
- 5x User Push buttons
- I/O:
- Power Supply:
- Others:
- Reverse polarity of supply voltage protection
- Under/Over voltage protection5 x user buttons
Block Diagram
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add drawIO object here.
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anchor | Figure_OV_BD |
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title | TEI0009 block diagram |
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draw.io Diagram |
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border | false |
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viewerToolbar | true |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 57 |
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diagramName | TEI0009_OV_BD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramWidth | 641 |
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- Barrel Jack, J12
- RJ45 socket, J8...9
- VGA SocketD-Sub Connector, J11
- Push button(Reset), S7
- Grove connector, J5
- Under/Over Voltage ProtectorProtecter, U9
- 7-segment LED, D11
- 1x6 pin header, J4
- 1x8 pin header, J2...3
- User Red LEDs, D2...9
- 8x User Red LEDs, D13...17
- 5x User Push buttons, S1- S3...6
- Red LED (CONF_DONE), D10
- PSRAM memory, U3
- SDRAM memory, U10
- Voltage Regulator, U5- U7
- AD/DA Convertor, U2
- Pmod 2x6 SMD host socket, P1...6
- Intel®Cyclone 10 LP, U1
- Config DeviceConfiguration memory, U5
- 1x10 pin header, J1
- EEEPROM, U15- U18- U20
- FTDI FT2232H USB2 to JTAG/UART adapter, U14
- Micro USB 2.0 receotacle 90, (receptacle) J10
- Push button (RST_GPIO), S2
- Oscillator, U22
- Ethernet PHY, U17- U19
- SPI QSPI Flash memory, U12
Initial Delivery State
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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SPI QSPI Flash | Not programmed |
| EEPROM | Programmed | FTDI configuration | SDRAM | Not programmed |
| PSRAM | Not programmedDDR3 SDRAM |
| FTDI System Controller CPLD | Not programmed |
| Configuration Memory | Demo Design | PSRAM | Config Device |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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anchor | Table_OV_RST |
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title | Reset process. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Signal | Connected to | Note |
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RESET | S1 S7 (Push button) | Connected to nCONFIG | RST_GPIO | S2 (Push button) |
| EXT_RST | J3 (1x8 pin header) Bank 2 |
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Signals, Interfaces and Pins
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TEI0009 has 6 PMod 2x6 SMD Host Socket 90° which are connected to Cyclon 10 LP (U1).
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anchor | Table_SIP_SMD |
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title | PMod SMD host socket information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Signals | Connected to | Notes |
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P1 | P1_IO1...8 | Bank 2 |
| P2 | P2_IO1...8 | Bank 2 |
| P3 | P3_IO1...8 | Bank 8 |
| P4 | P4_IO1...8 | Bank 8 |
| P5 | P5_IO1...8 | Bank 7 |
| P6 | P6_IO1...8 | Bank 7 |
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anchor | Table_SIP_RJ45 |
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title | RJ45 connectors information |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | ETH1 Pin | ETH2 Pin | Notes |
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TD+ | ETH_TX_P | U17- TXP | U19- TXP |
| CT | ETH_CTREF_TCT | - | - | Connected to GND | TD- | ETH_TX_N | U17- TXM | U19- TXM |
| RD+ | ETH_RX_P | U17- RXP | U19- RXP |
| CT | ETH_CTREF_RCT | - | - | Connected to GND | RD- | ETH_RX_N | U17- RXM | U19- RXM |
| LED Green | ETH_LED0 | U17- NWAYEN | U19- NWAYEN |
| LED Yellow | ETH_LED1 | U17- SPEED | U19- SPEED |
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D-Sub Connectors
VGA host socket is connected TEI0009 is equipped with a D-Sub connector (Receptacle) which provides interface to Cyclone 10 LP through Bank 2.
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anchor | Table_OBP |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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QSPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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Part number: IS66WVH8M8BLL
Supply voltage: 3.3 V
- Clock Frequency: 100MHz
Temperature: -40°C ~ 85°C
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7 Segment
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LED
the The TEI0009 has a LED 7 Segment- 4 Digit which is connected to Bank 6.
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TEI0009 has three EEPROM, U15, U18 and U20. U15 containt is pre-programmed by FTDI FT2232H configuration.
Scroll Title |
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pinsFTDI and EEPROM pin connections |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Pin | Schematic | Connected to | Notes |
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Grove HeaderNotesU18, U20 | SCL | I2C_SCL | Bank 6 | J5 | EECS | U14 (FTDI) |
| CLK | |EECLK | U14 (FTDI) |
| DIN/DOUT | EEDATA | U14 (FTDI) | FTDI Configuration |
SDA | I2C_SDA | Bank 6 | J5
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anchor | Table_OBP_I2C_EEPROMEEP |
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title | I2C address for EEPROM interface MIOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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I2C AddressDesignatorNotes0x50U180x52 |
LEDs
SCL | I2C_SCL | Bank 6 | J5 |
| SDA | I2C_SDA | Bank 6 | J5 |
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anchor | Table_OBP_I2C_LEDEEPROM |
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title | On-board LEDsI2C address for EEPROM |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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SchematicDesignator ColorConnected toActive Level
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LEDs
Scroll Title |
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Schematic | Designator | Color | Connected to | Active Level | Note |
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LED1...8 | D2...9 | Red | Bank 3 | High |
| LED_PB1 | D13...17 | Red | Bank | Note | LED1...8 | D2...9 | Red | Bank 3 | High | LED_PB1 | D13...17 | Red | Bank 7 | High |
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CONF_DONE | D10 | Red | Bank 6 | Low |
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Power supply with minimum current capability of xx A 1A for system startup is recommended.
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Scroll Title |
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anchor | Table_PWR_PC |
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title | Power Consumption |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Input PinFPGA | Typical Current |
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Intel Cyclone 10 LP FPGA | VIN | TBD* |
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* TBD - To Be Determined
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Scroll Title |
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anchor | Table_RH_HRH |
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title | Hardware Revision History |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Revision | Changes | Document Link |
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2018-2-19 | 01 | - | REV01 | 2018-7- | 0918 | 02 | - Change J5 from SMD connector to GROVE connector
- Connect clock 12 MHz to Bank 1
- Connect I2C SLA/SDA to Bank 3
- Remove SMA Coaxial straight J19,J20
- Remove DIP Switch S1
- Add 5 red LEDs
- Add 2 Push buttons
- Add 64 Mbit QSPI flash memory
- Change SDRAM memory, 143 MHz to 166 MHz
- Remove 10bit ADC
- Remove 10bit DAC
- Add 12bit DAC/ADC
- Remove SMA Coaxial straight J19,J20
- Remove SMA Coaxial straight J19,J20
- Remove Tranciever USB
- Remove DIP switch S2
- Different Power Dependencies
- Remove 24MHz Oscillator
- Add 4x Pmod SMD host socket
| REV02 | 02
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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
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