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| Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
There is a 64MBit QSPI Flash memory (U12) provided by Winbond which can be used to store data or configuration.
| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pin | Schematic | Connected to | Notes |
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| CS | F_CS | Bank 7 |
| | CLK | F_CLK | Bank 7 |
| | IO0...3 | F_IO0...3 | Bank 7 |
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| Page properties |
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0009 has 64 Mb volatile 256 MBit volatile provided by Winbond , SDRAM IC(U10) for storing user application code and data. Up to 512 MBit SDRAM is possibleon other assembly option.
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The TEI0009 is integrated with 64Mbit Pseudo Static Random Access Memory (SDRAMPSRAM) using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation.
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| Scroll Title |
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| anchor | Table_OBP_FTDI |
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| title | FTDI chip interfaces and pins |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FTDI Chip Pin | Signal Schematic Name | Connected to | Notes |
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| ADBUS0 | TCK | Bank 1 | JTAG interface | | ADBUS1 | TDI | Bank 1 | | ADBUS2 | TDO | Bank 1 | | ADBUS3 | TMS | Bank 1 | | BDBUS0 | BDBUS0 | Bank 6 |
| | BDBUS1 | BDBUS1 | Bank 6 |
| | BDBUS2 | BDBUS2 | Bank 6 |
| | BDBUS3 | BDBUS3 | Bank 6 |
| | BDBUS4 | BDBUS4 | Bank 6 |
| | BDBUS5 | BDBUS5 | Bank 6 |
| | EECS | EECS | U15 (EEPROM) | EECLK | EECLK | U15 (EEPROM) | EEDATA | EEDATA | U15 (EEPROM) | OSCI | CK12M | U16 (12MHz Oscillator) | DM | D_N | J10 (Micro USB2.0) | DP | D_P | J10 (Micro USB2.0) | U15 (EEPROM) |
| | EECLK | EECLK | U15 (EEPROM) |
| | EEDATA | EEDATA | U15 (EEPROM) |
| | OSCI | CK12M | U16 (12MHz Oscillator) |
| | DM | D_N | J10 (Micro USB2.0) |
| | DP | D_P | J10 (Micro USB2.0) |
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Configuration Memory
On-board serial configuration memory (U5) is provided by Intel with 16 MBit (2 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 interface.
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | FTDI and EEPROM pin connections |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pin | Signal Schematic Name | Connected to | Notes |
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| DATA1 | AS_DATA0 | U1, Bank 1
| Data out | | DATA0 | AS_ASDO | U1, Bank 1 | Data in | | nCS | AS_NCS | U1, Bank 1 | chip select | | DCLK | AS_DCLK | U1, Bank 1 | clock |
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Ethernet PHY
The TEI0009 is equipped with two Ethernet PHY (U19, U17) which are connected to two RJ45 connectors.
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| Scroll Title |
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| anchor | Table_TS_ROC |
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| title | Recommended operating conditions. |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
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| Parameter | Min | Max | Units | Reference Document |
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| VIN | 4.75 | 5.25 | V |
| | VCCIO | 3.135 | 3.465 | V | See Cyclone 10 LP datasheet. | | VCCINT | 1.15 | 1.25 | V | See Cyclone 10 LP datasheet. | | VCCD_PLL | 1.15 | 1.25 | V | See Cyclone 10 LP datasheet. | | VCCA | 2.375 | 2.625 | V | See Cyclone 10 LP datasheet. | | V_AN | 0 | 3.3 | V | See AD5592RBCPZ datasheet. | | V_DIG | 0 | 3.3 | V | See AD5592RBCPZ datasheet. | | V_REF_IN | 1 | 3 | V | See AD5592RBCPZ datasheet. | | V_REF_EX | 2.45 | 2.55 | V | See AD5592RBCPZ datasheet. | | T_OP | 0 | 8570 | °C | See Cyclone 10 LP SDRAM W9864G6JT datasheet. |
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Physical Dimensions
Module size: 95 mm × 110 mm. Please download the assembly diagram for exact numbers.
- PCB thickness: 1.6 mm.
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