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  • Single 3.3V input (Direct modules power supply)
  • Header for TE0790 JTAG/UART Adapter
  • 20 Pin ARM JTAG header (connected to MIO JTAG 0)
  • 10 Pin I2C header for Silabs Clock Builder Field Programmer
  • Done, Error /and Status LEDs
  • One PL GT with SMA connectors
  • One PS GT with SMA connectors
  • GT local loopback
  • PL I/O loopbacks
  • PS I/O loopbacks
  • Boot Mode switches
  • Power control switches to control TE080x power domains
  • One pre-assembled TE0790 XMOD FTDI JTAG adapter

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Scroll Title
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titleTEBT0808 block diagramBlock Diagram


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titleTEBT0808 main componentsMain Components


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  1. Uninsulated 2 mm rigid socketNon-insulated Jack. J8-J7
  2. SMA Coaxial straight. J6- J9...15
  3. Surface Mount Schottky Barrier Rectifier. D1
  4. Box Headers, Straight/Angled J5-J16
  5. Board to Board Connector. J1...4
  6. Clock Oscillator, U2
  7. On-Board LED, D2...4
  8. DIP-Switch, S1...3
  9. XMOD JTAG Base,  JX1

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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titleBoot processProcess.

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M3M2M1M0Bootmode HexBootmodeNotes
ONONONON0x00xFPS Main JTAG (TE0790 USB JTAG)
ONONOFFON0x20xDSPI Flash (dual parallel, 4bit x 2, 32bit Addressing)
ONOFFOFFOFF0x8PJTAG(MIO29:26)


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titleReset processProcess.

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Signal

B2BNote

PLL_RST

J2-89
SRST_BJ2-96connected Connected to PJTAG0_SRST - J16


Signals, Interfaces and Pins

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Scroll Title
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titleGeneral PL I/O to B2B connectors information

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B2B ConnectorInterfacesNumber of I/ONotes
J1

User I/O

22 singel endedSingle Ended, 11 Differential

8 singel endedSingle Ended, 4 Differential

8 singel endedSingle Ended, 4 Differential

8 singel endedSingle Ended, 4 Differential

3 singel endedSingle Ended

Connected to Bank 66

Connected to Bank 228

Connected to Bank 229

Connected to Bank 230

VCCO_66, PL_1V8

J2

Ethernet PHY

32 singel endedSingle Ended, 16 Differential

4 singel endedSingle Ended, 16 Differential

Connected to Bank 505

Connected to Bank 128

Control Signals15 single endedSingle EndedPLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE
Power Control Signal10 single endedSingle EndedEN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L
JTAG Interface7 single endedSingle EndedTCK, TDI, TMS, TDO, MR, Rxd, Txd
WANNE22 single endedSingle EndedPLL_SCL, PLL_SDA
Clock

6 singel endedSingle Ended, 3 Differential

CLK0, CLK7, CLK8

J3



User I/O

12 singel endedSingle Ended, 6 Differential

12 singel endedSingle Ended, 6 Differential

Connected to Bank 48

Connected to Bank 47

Clock6 singel endedSingle Ended, 3 DifferentialCLK228, CLK229, CLK230
PJTAG Interface7 single endedSingle EndedPJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO,
MIO27 single endedSingle EndedMIO19..76
UART2 single endedSingle EndedTXD, RXD
Power pins4 single endedSingle EndedPS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47
J4User I/O

48 singel endedSingle Ended, 62 Differential

4 single endedSingle Ended

Connected to Bank 64

Connected to Bank 64

Power pins4 single endedSingle EndedVCCO_64, VCCO65



XMOD JTAG

JTAG access to the TE080x  UltraSoM+ TEBT0808  is available through B2B connector JM2 .

TODO XMOD Pin Header and recommended XMOD DIP setting and used MIO on B2B connector

PJTAG

TODO Pin Header

SI I2C Pinheader

TODO Pin Header

SMA

TODO Pin Header

Test Points

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using XMOD JTAG adapter TE0790 adapter.

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titleJTAG Pins Connection

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JTAG Signal

B2B Connector

Notes
TMSJ2- 126
TDIJ2- 122
TDOJ2- 124
TCKJ2- 120


There is a DIP switch on TE0790 adapter which must be set accordingly.

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title Xmod Adapter DIP-Switch Setting Description

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DIP SwitchONOFFDefaultDescription
1Normal modeAdapter board CPLD update modeONUpdate Mode JTAG access to SC CPLD only
2Do not use (illegal setting)Normal modeOFFMust be always in OFF state.
3VIO connected to 3.3VPower VIO from pin header J2OFFUser I/O Voltage
4Power 3.3V from USBPower 3.3V from pin header J2OFFPower on-board peripherals (FTDI chip & SC CPLD, ...)


The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) can be configured by the DIP-switches 3 and 4:

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title Xmod Adapter DIP-Switch Setting Description

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DIP Switch-3DIP Switch-43.3V (VCC) Pin 5VIO Pin 6Description
OFFOFF3.3V from base (input**)VIO from base (input**)3.3V (pin 5) and VIO (pin 6) sourced from base
OFFON3.3V from USB* (output**)VIO from base (input**)VIO sourced from base by Pin 6
ONOFF3.3V from base (input**)3.3V from base (input**)VIO and 3.3V source by base (Pin 5 and Pin 6 are shorted and both must be sourced by 3.3V)
ONON3.3V from USB* (output**)3.3V from USB* (output**)

3.3V (pin 5) and VIO (pin 6) sourced USB (Pin 5 and Pin 6 are shorted and both are 3.3V)


PJTAG

PJTAG access to the TEBT0808  is available through B2B connector JM3.

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titlePJTAG Pins Connection

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JTAG Signal

B2B Connector

Notes
TMSJ3- 94
TDIJ3- 90
TDOJ3- 92
TCKJ3- 88
SRSTJ2- 96Connected to SRST_B


I2C Pin header

I2C signals can be accessed through pin header J5.

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titleI2C Connections

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Signals

B2B Connector

Pin Header Notes
PLL_SCLJ2- 90J5- 3
PLL_SDAJ2- 92J5- 7


SMA Coaxial

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titleSMA Connections

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Designator

Signals

B2B Connector

Notes
J6B230_TX3_PJ1-2
J9B230_RX3_NJ1-5
J10B230_RX3_PJ1-3
J11B230_TX3_NJ1-4
J12B505_TX0_NJ2-67
J13B505_TX0_PJ2-69
J14B505_RX0_NJ2-70
J15B505_RX0_PJ2-72


Test Points

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titleTest Points Information

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Test Point

Signals

B2B Connector

Notes
1DDR_1V2J2-135
2PG_PSGTJ2-82
3ERR_STATUSJ2-86
4PLL_FDECJ2-94
5EN_LPDJ2-108
6EN_DDRJ2-112
7PG_PLJ2-104
8PG_PLL_1V8J2-80
9N_PSGTJ2-84
10ERR_OUTJ2-88
11EN_FPDJ2-102
12LP_GOODJ2-106
13PG_FPDJ2-110
14PG_DDRJ2-114
15EN_PLL_PWRJ2-77
16PLL_FINCJ2-81
17PG_GT_RJ2-91
18EN_GT_RJ2-95
19EN_PLJ2-101
20EN_GT_LJ2-79
21PLL_SEL0J2-93
22PG_GT_LJ2-97
23INIT_BJ2-98
24IN1_PJ2-4
25PLL_SEL1J2-87
26PLL_LOLNJ2-85
27PLL_RSTJ2-89
28DX_PJ2-119
29DX_NJ2-121
30IN1_NJ2-6
31B505_CLK0_PJ2-10
32B505_CLK0_NJ2-12
33B505_CLK1_PJ2-16
34B505_CLK1_NJ2-18
35B128_CLK1_PJ2-22
36B128_CLK1_NJ2-24
37CLK0_NJ2-1
38CLK0_PJ2-3
39CLK8_PJ2-7
40CLK8_NJ2-9
41CLK7_PJ2-13
42CLK7_NJ2-15
43IN2_PJ3-66
44IN2_NJ3-68
45B230_CLK1_NJ3-59
46B230_CLK1_PJ3-61
47B229_CLK0_NJ3-65
48B229_CLK0_PJ3-67
49PLL_3V3J3-152
50GNDJ3-155
51PL_1V8J1-121
52PS_1V8J3-147
53SI_PLL_1V8J3-151
54PROG_BJ2-100
55...56GND-



On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

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Scroll Title
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titleOn board peripheralsBoard Peripherals

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Chip/InterfaceDesignatorNotes
DIP SwitchS1...3
LEDsD2...4
OscillatorU2125.00 MHz



DIP Switch

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Control signals must be set by using DIP Switch S2, S3.

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titleDIP Switch S2

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SignalsB2BS2 switchNotes
EN_PSGTJ2-84S2A
EN_GT_RJ2-95S2B
EN_GT_LJ2-97S2C
EN_PLL_PWRJ2-77S2Dconnected to PG_PL


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titleModule power rails.

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Power Rail Name

B2B

JM1 Pin

B2B

JM2 Pin

B2B

JM3 Pin

B2B

JM4 Pin

DirectionNotes
3.3V151,153,155,157,159140,142,144,146154,156,158,160,
153,155,157,159		157,158,159,160-OutputCarrier power supply to module power rails PL_DCDCIN. DCDCIN, LP_DCDC, GT_DCDC, PL_3V3V

VCCO_47

--43, 44-OutputConnected to 1.8 (SI_PLL_1V8)
VCCO_48--15,16-OutputConnected to 1.8 (SI_PLL_1V8)
VCCO_64---58, 106OutputConnected to 1.8 (PL_1V8)
VCCO_65---69, 105OutputConnected to 1.8 (PL_1V8)
VCCO_6690,120---OutputConnected to 1.8 (PL_1V8)
PS_1V8-99,147, 148-Input
PLL_3V3--152-Output3.3V
PL_1_V8121,121---Input1.8V for PL Banks
SI_PLL_1V8--151-Input
DDR 1V2-135--Inout
PL_3V3--152-OutputConnected to 3.3V
PSBAT-125--Output1.2V..1.5V, abs. max 2V


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Scroll Title
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titleRecommended operating conditions.

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SymbolsMinMaxUnitNote
VIN3,143.47VImportant, check also TRM of the connected module
Operating Temperatur




Physical Dimensions

  • Module size: 90 mm × 90 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 3.5 mm.

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