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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables


      • Scroll Title
        anchorTable_tablename
        titleText

        Scroll Table Layout
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        sortEnabledfalse
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        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.


Scroll pdf ignore

Table of Contents

Table of Contents

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The Trenz Electronic TE0802 is an evalution modulea development board integrating a Xilinx Zynq UltraScale+ . Other assembly options for the FPGA and the memory chips are available. Please contact us for further information.

Refer to http://trenz.org/te0802-info for the current online version of this manual and other available documentation.

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Notes :

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Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

  • MPSoC: Xilinx Zynq   XCZU2CG -1SBVA484E
  • SDRAM: LPDDR4-3733 8Gb 256Mx32 
  •  Xilinx Zynq UltraScale+ MPSoC
    • Package: 1SBVA484E
    • Speed Grade: -1 (Slowest)

    • Temperature Grade: Extended (0 to +100 °C)

  • RAM/Storages:
    • SDRAM: LPDDR4 8Gb 256Mx16x 2 
    • SPI Flash 
    Storages:
    • SPI Flash 256Mb (32M x 8) 133MHz
    • microSD Card
    • M.2 SSD PCIe
    •  133 MHz
    • EEPROMs 2Kb (256 x 8)
    • EEPROMs 4Kb (512 x 8)
  • Display Interfaces: 
    • DisplayPort
    • VGA
    • 4 Digit 7-Segment LED
    • 8 LEDs
  • Audio:
    • 3.5mm Jack (PWM Output)
    • USB JTAG/UART microUSB
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
    • microSD Card
    • M.2 SSD PCIe
    • 3.5 mm Earphone Jack (PWM Output)
    • Display Port
    • VGA
    • 4 Digit 7-Segment LED Display
    • 8 LEDs
    Input:
    • 5 User Buttons
    • 8 Bit Slide Switches
    • Reset Button
  • User I/O:
    • 2x PMOD Connectors
  • Communication:
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
  • Debug
    • USB JTAG/UART microUSB
    • 2x Pmod Connector
  • Power
    • 5 V
    Power
    • 5V +/- 10%
    • ~3.5W5 W
  • Dimension: 100mm x 100mm

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
anchorFigure_OV_BD
titleTE0802 Block Diagram


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Image RemovedImage Added


Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .


...

Scroll Title
anchorFigure_OV_MC
titleTExxxx main componentsTE0802 Main Components (Picture shows Revision 01)


Scroll Ignore

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  1. Power Jack, J13
  2. RJ45 Socket, J4
  3. VGA, J7
  4. Push Button (Reset), BTN6
  5. Grove Connector, J5
  6. Undervoltage/Overvoltage Protector, U9
  7. 7-Segment LED, D11
  8. 1x6 Pin Header, J4
  9. 1x8 Pin Header, J2...3
  10. 8x User LEDs (Red), D2...9
  11. 5x User LEDs (Red), D13...17
  12. 5x User Push Buttons, S1 - S3...6
  13. Red LED (CONF_DONE), D10
  14. PSRAM Memory, U3
  15. SDRAM Memory, U10
  16. Voltage Regulator, U4 - U7
  17. AD/DA Converter, U2
  18. 6x Pmod Host Socket, P1...6
  19. Xilinx Zynq UltraScale+ MPSoc, U14
  20. Serial Configuration Memory, U5
  21. 1x10 Pin Header, J1
  22. EEPROM, U15 - U18 - U20
  23. FTDI USB 2 to JTAG/UART Converter, U14
  24. Micro USB 2.0, J10
  25. Push Button (RST_GPIO), S2
  26. Oscillator, U22
  27. Ethernet PHY, U17 - U19
  28. QSPI Flash Memory, U12
  1. Xilinx Zynq UltraScale+ MPSoc, U14
  2. Oscillator, U15, U7
  3. Slide Switch, S1
  4. Headphone Jack, J12
  5. SPI Flash Memory, U16
  6. EEPROM, U2
  7. LPDDR4 SDRAM, U13
  8. DisplayPort, J3
  9. M.2 Key M PCIe x1, U5
  10. Ethernet PHY, U6
  11. RJ45 Socket, J4
  12. Grove Connector, J10
  13. Pmod Host Socket, J5...6
  14. D-Sub Connector, J7
  15. DIP Switch, S7...8
  16. Push Button, BTN1...5

Initial Delivery State

...

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

Image Added


  1. Xilinx Zynq UltraScale+ MPSoc, U14
  2. LPDDR4 SDRAM, U13
  3. M.2 Key M PCIe x1, U5
  4. SPI Flash Memory, U16
  5. EEPROM, U2, U18
  6. Oscillator, U15, U7, U19, U23, U43
  7. Clock Generator, U8
  8. Clock Generator Programming Connector, J14
  9. Grove Connector, J10
  10. Pmod Host Socket, J5...6
  11. Headphone Jack, J12
  12. D-Sub Connector, J7
  13. DisplayPort, J3
  14. RJ45 Socket, J4
  15. Ethernet PHY, U6
  16. USB Type A, J11
  17. USB 2.0 PHY, U22
  18. Micro USB 2.0 Type B, J8
  19. FTDI USB 2.0 to JTAG/UART Converter, U17
  20. microSD Card, J9
  21. Slide Switch, S1
  22. Push Button, BTN1...5
  23. DIP Switch, S7...8
  24. 4 Digit 7-Segment LED Display, D9
  25. 8x LEDs (Red), LED0...7
  26. Power Jack, J13
  27. Overvoltage/Undervoltage/Reverse Supply Protector, U12
  28. Power Management Integrated Circuit (PMIC), U1, U9
  29. Power Good LED (Green), D12

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


Scroll Title
anchorTable_OV_IDS
titleInitial Delivery State of Programmable Devices on the Module

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Storage device name

Content

Notes

SPI Flash (U16)

Not programmed


EEPROM (U2)Not programmedExcept Ethernet MAC
EEPROM (U18)Programmed

FTDI Configuration

LPDDR4 SDRAM (U13)Not programmed


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

Bootmode signals must be set through DIP Switch S1. 

...

Scroll Title
anchorTable_OV_IDSBP
titleInitial delivery state of programmable devices on the moduleBoot Process

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Storage device name

Content

Notes

Quad SPI Flash

EEPROMDDR3 SDRAMSystem Controller CPLD

Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

MODE Signal State

MODE1

S1-2(B)

MODE0

S1-1(A)

Boot Mode

MODE[2:0]=000

OFFOFF

JTAG

MODE[2:0]=001

OFFONnot supported

MODE[2:0]=010

ONOFFQSPI(32 bit)

MODE[2:0]=011

ONONSD0(2.0)


Reset setting is available through Push Button BTN6.

Scroll Title
anchorTable_OV_BPRST
titleBoot process.Reset Process

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MODE

Signal

State

Boot Mode
Scroll Title
anchorTable_OV_RST
titleReset process.
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Signal

B2BI/ONote
Connected toNote

POR_B

BTN6, Push ButtonConnected to nRESET


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

...

I/Os on Pin Headers and Connectors

FPGA bank number and number of I/O signals connected to the B2B connectorconnectors:

Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors informationPin Header and Connectors Information

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FPGA Bank
B2B Connector
Connector I/O Signal CountVoltage LevelNotes

...

JTAG access to the TExxxx SoM through B2B connector JMX.

...

anchorTable_SIP_JTG
titleJTAG pins connection
Bank 503Micro USB, J8 (over FTDI)4 Single Ended3.3 VJTAG
Bank 500Micro USB, J8 (over FTDI)2 Single Ended3.3 VUART
Bank 500Micro SD Card, J97 Single Ended3.3 V
Bank 502ETH RJ45, J4 (over ETH PHY)14 Single Ended1.8 V
Bank 505, 502USB 3.0, J11 (USB2 over USB PHY)2 Differential Pairs, 12 Single Ended-- / 1.8V

Bank 505, 501

SSD M.2, U5

2 Differential Pairs, 5 Single Ended

-- / 3.3 V


Bank 505, 501Display Port Connector, J32 Differential Pairs, 5 Single Ended--/ 3.3 V
Bank 26, 65, 66,D-Sub Host Socket (VGA), J714 Single Ended3.3 V / 1.8 V / 1.8 V
Bank 65Earphone, J123 Single Ended1.8 V
Bank 500Grove Connector, J102 Single Ended3.3 V
Bank 26Pmod Host Socket, J58 Single Ended3.3 V
Bank 26Pmod Host Socket, J6 8 Single Ended3.3 V


Micro SD Card

TE0802 is equipped with a micro SD card connector (J9).

Scroll Title
anchorTable_SIP_SD
titleMicro SD Card Connector Information

...

JTAG Signal

...

B2B Connector

...

MIO Pins

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

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MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI
Scroll Title
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titleMIOs pins

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MIO Pin
SchematicConnected to
B2B
Notes

...

SD_DAT0

MIO 13, FPGA Bank 500


SD_DAT1MIO 14, FPGA Bank 500
SD_DAT2MIO 15, FPGA Bank 500
SD_DAT3MIO 16, FPGA Bank 500
SD_CLKMIO 22, FPGA Bank 500
SD_CMDMIO 21, FPGA Bank 500
SD_CDMIO 24, FPGA Bank 500


RJ45 Connector

TE0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connector J4 is connected to Ethernet PHYs U6.

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Designator
Scroll Title
anchorTable_OBPSIP_RJ45
titleOn board peripheralsRJ45 Connector Information

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PinSchematicETH Pin
Chip/Interface
Notes

Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

...

anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins
2PHY_MDI0_PMDIP[0]
3PHY_MDI0_NMDIN[0]
4PHY_MDI1_PMDIP[1]
5PHY_MDI1_NMDIN[1]
6PHY_MDI2_PMDIP[2]
7PHY_MDI2_NMDIN[2]
8PHY_MDI3_PMDIP[3]
9PHY_MDI3_NMDIN[3]


USBs Sockets

TE0802 is equipped with a Micro USB2.0 B connector J8 and a USB3.0 connector J11.

FTDI FT2232 (U17) can be accessed through Micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.

Scroll Title
anchorTable_SIP_USB2
titleUSB2.0 B Socket Information

Scroll Table Layout
orientationportrait

...

Scroll Title
anchorTable_OBP_RTC
titleI2C interface MIOs and pins

Scroll Table Layout
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MIO
USB2.0 PinSchematic
U? Pin
Connected toNotes
D-D_N

FTDI, U17


D+D_PFTDI, U17
VbusUSB_VBUSGND
Notes



scroll
Scroll Title
anchorTable_OBPSIP_I2C_RTCUSB3
titleI2C Address for RTCUSB3.0 A Socket Information

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MIO
USB3.0 Pin
I2C Address
Schematic
Designator
Connected toNotes

...

titleTableOBPEEPNotes
D-
anchor
USB0_
D_
titleI2C EEPROM interface MIOs and pins
Scroll Table Layout
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MIO PinSchematicU?? Pin
NUSB PHY, U22
D+USB0_D_PUSB PHY, U22
StdA_SSRX-USB_RX2_NFPGA Bank 505
StdA_SSRX+USB_RX2_PFPGA Bank 505
StdA_SSTX-USB_TX2_NFPGA Bank 505
StdA_SSTX+USB_TX2_PFPGA Bank 505
VBUSVBUSUSB PHY, U22


SSD M.2 Connector

TE0802 is equipped with a SSD M.2 connector (U5).

Scroll Title
anchorTable_OBPSIP_I2C_EEPROMSSD
titleI2C address for EEPROMSSD M.2 Connector Information

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repeatTableHeadersdefaultstyle
widthssortByColumn1
sortEnabledfalse
cellHighlightingtrue

MIO
Pin
I2C Address
Schematic
Designator
Connected toNotes

LEDs

...

anchorTable_OBP_LED
titleOn-board LEDs
PERn0/SATA-B+

SSD_RX3_N

Pin M22, FPGA Bank 505
PERp0/SATA-B-SSD_RX3_PPin M21, FPGA Bank 505
PERn0/SATA-A+

SSD_TXC3_N

Pin K22, FPGA Bank 505
PERp0/SATA-A-SSD_TXC3_PPin M21, FPGA Bank 505
REFCLKN

SSD_RCLK_N

Pin 9, Clock Generator U8
REFCLKPSSD_RCLK_PPin 10, Clock Generator U8
DAS/DSS#SSD_DASMIO35, FPGA Bank 501
DEVSLPSSD_SLEEPMIO32, FPGA Bank 501
PERST#SSD_PERSTnMIO31, FPGA Bank 501
CLKREQ#SSD_CLKRQMIO33, FPGA Bank 501
PEWake#SSD_WAKEMIO34, FPGA Bank 501


Display Port Connector

TE0802 is equipped with a Display Port connector (J3).

...

DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

Scroll Title
anchorTable_OBPSIP_ETHDP
titleEthernet PHY to Zynq SoC connectionsDisplay Port Socket Information

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Bank
Schematic
Signal NameETH1ETH2Signal Description

CAN Transceiver

...

anchorTable_OBP_CAN
titleCAN Tranciever interface MIOs

...

Corresponding SignalsConnected toNotes
DP_TX_L0_P/NDP0_TX_P/NPin A19/A20, FPGA Bank 505
DP_TX_L1_P/NDP1_TX_P/NPin C19/C20, FPGA Bank 505
DP_TX_AUX_P/NDP_AUX_TX/RXMIO27, MIO30, FPGA Bank 501


D-Sub Connector

TE0802 is equipped with a D-Sub connector (J7).

...

Scroll Title
anchorTable_OBPSIP_CLKVGA
titleOsillatorsD-Sub Connector Information

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Designator
Schematic
Description
Corresponding Signals
Frequency
Connected to
Note
Notes
MHzMHzKHz

Power and Power-On Sequence

...

hiddentrue
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

VGA_REDVGA_R0...3Bank 65Red Channel
VGA_GREENVGA_G0...3Bank 65Green Channel
VGA_BLUEVGA_B0...3Bank 66Blue Channel
VGA_RGB_HSYNCVGA_HSBank 26Horizontal Sync
VGA_RGB_VSYNCVGA_VSBank 26Vertical Sync


Headphone Connector

TE0802 is equipped with a headphone connector (J12).

Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

Scroll Title
anchorTable_PWRSIP_PCHP
titlePower ConsumptionHeadphone Connector Information

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefaultstylewidths
sortByColumn1sortByColumn1
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Power Input PinTypical Current
VINTBD*

* TBD - To Be Determined

...

SchematicConnected toNotes
JACKSNSPin F3, FPGA Bank 65
PWM_RPin F4, FPGA Bank 65
PWM_LPin E3, FPGA Bank 65


Grove Connector

TE0802 is equipped with a grove connector (J10).

Scroll Title
anchorFigureTable_PWRSIP_PDGrove
titlePower DistributionGrove Connector Information

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Power-On Sequence

...

anchorFigure_PWR_PS
titlePower Sequency
Scroll Ignore

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SchematicConnected toNotes
Grove_SCL0MIO18, FPGA Bank 500
Grove_SDA0MIO19, FPGA Bank 500


Pmod Sockets

TE0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.

Voltage Monitor Circuit

Scroll Title
anchorFigureTable_PWRSIP_VMCPMOD
titleVoltage Monitor CircuitPmod SMD Host Socket Information

scroll-

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Power Rails

tablelayout
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Scroll Title
anchorTable_PWR_PR
titleModule power rails.

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Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

...

DesignatorSignalsConnected to Notes
J5PMOD_A0...7Bank 26
J6PMOD_B0...7Bank 26


Test Points

Voltage
Scroll Title
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titleZynq SoC bank voltages.Test Points Information

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Test Point

Signals

Bank          

Schematic Name
Notes