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The Trenz Electronic TE0802 is an evalution modulea development board integrating a Xilinx Zynq UltraScale+ . Other assymbly assembly options for the FPGA and the memory chips are available. Please ask contact us for further information.

Refer to http://trenz.org/te0802-info for the current online version of this manual and other available documentation.

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Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

  • MPSoC: Xilinx Zynq XCZU2CG-1SBVA484E  XCZU2CG - Xilinx Zynq UltraScale+ MPSoC
    • Package: 1SBVA484E
    • Speed Grade: -1 (Slowest)

    • Temperature Grade: Extended (0 to +100 °C)

  • RAM/Storages:
    • SDRAM: LPDDR4
    -3733
    • 8Gb
    256Mx32
    • 256Mx16x 2 
    Storages:
    • SPI Flash 256Mb (32M x 8) 133 MHz
    • microSD Card
    • M.2 SSD PCIe
    • EEPROMs 2Kb (256 x 8)
    • EEPROMs 4Kb (512 x 8)
  • Display Interfaces: 
    • DisplayPort
    • VGA
    • 4 Digit 7-Segment LED Display
    • 8 LEDs
    Audio:
    • USB JTAG/UART microUSB
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
    • microSD Card
    • M.2 SSD PCIe
    • 3.5 mm Earphone Jack (PWM Output)
    Input:
    • Display Port
    • VGA
    • 4 Digit 7-Segment LED Display
    • 8 LEDs
    • 5 User Buttons
    • 8 Bit Slide Switches
    • Reset Button
    User I/O:
    • 2x Pmod Connector
    Communication:
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
    Debug
    • USB JTAG/UART microUSB
  • Power
    • 5 V +/- 10%
    • ~3.5 W
  • Dimension: 100mm x 100mm

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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titleTE0802 Block Diagram


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Main Components

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  • Overview of Boot Mode, Reset, Enables.

Bootmode signals must be set through DIP Switch S1. 

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MODE Signal State

MODE0

MODE1

S1-

1MODE1

2(B)

MODE0

S1-

2

1(A)

Boot Mode

MODE[

1

2:0]=

00b

000

OFFOFF

JTAG

MODE[

1

2:0]=

01b

001

OFFON
-
not supported

MODE[

1

2:0]=

10b

010

ONOFFQSPI(32 bit)

MODE[

1

2:0]=

11b

011

ONONSD0(2.0)


Reset setting is available through Push Button BTN6.

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Signal

Connected toNote

POR_B

BTN6, Push ButtonConnected to nRESET


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U5
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FPGA BankConnector I/O Signal CountVoltage LevelNotes
Bank 503
J8
Micro USB, J8 (
Micro USB
over FTDI)4 Single Ended3.3 VJTAG
Bank 500
J8
Micro USB, J8 (
Micro USB
over FTDI)2 Single Ended3.3 VUART
Bank 500
J9, (
Micro SD Card
)
, J97 Single Ended3.3 V
Bank 502ETH RJ45, J4
,
(
RJ45
over ETH PHY)14 Single Ended1.8 V
Bank 505, 502
J11, (
USB 3.0, J11 (USB2 over USB PHY)2 Differential Pairs
0.85 V
, 12 Single Ended-- / 1.8V

Bank 505, 501

U5, (
SSD M.2
)
, U5

2 Differential Pairs

0.85 V

Bank 501

,

(SSD M.2)

5 Single Ended

-- / 3.3 V


Bank 505, 501
J3, (
Display Port Connector
)
, J32 Differential Pairs
0.85 VBank 26J7, (D-Sub Host Socket)2
, 5 Single Ended--/ 3.3 V
Bank 26, 65, 66,
J7, (
D-Sub Host Socket (VGA), J7
12
14 Single Ended3.3 V / 1.8 V / 1.8 V
Bank 65Earphone, J12
, Headphone
3 Single Ended1.8 V
Bank 500
J10, (
Grove Connector
)
, J102 Single Ended3.3 V
Bank 26
J5 (
Pmod Host Socket
)
, J58 Single Ended3.3 V
Bank 26
J6 (
Pmod Host Socket
)
, J6 8 Single Ended3.3 V

Micro USB 2.0

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Micro SD Card

TEI0802 TE0802 is equipped with a micro SD card connector (J9).

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SchematicConnected toNotes
SD_DAT0

MIO 13, FPGA Bank 500


SD_DAT1MIO 14, FPGA Bank 500
SD_DAT2MIO 15, FPGA Bank 500
SD_DAT3MIO 16, FPGA Bank 500
SD_CLKMIO 22, FPGA Bank 500
SD_CMDMIO 21, FPGA Bank 500
SD_CDMIO 24, FPGA Bank 500


RJ45 Connector

TEI0802 TE0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connectors connector J4 is connected to Ethernet PHYs U6.

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PinSchematicETH PinNotes
2PHY_MDI0_PMDIP[0]
3PHY_MDI0_NMDIN[0]
4PHY_MDI1_PMDIP[1]
5PHY_MDI1_NMDIN[1]
6PHY_MDI2_PMDIP[2]
7PHY_MDI2_NMDIN[2]
8PHY_MDI3_PMDIP[3]
9PHY_MDI3_NMDIN[3]

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USBs Sockets

TEI0802 TE0802 is equipped with a USB connector (J11).Micro USB2.0 B connector J8 and a USB3.0 connector J11.

FTDI FT2232 (U17) can be accessed through Micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.

MIO 52...63 FPGA Bank 502
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USB2.0 PinSchematic
Corresponding Signals
Connected toNotes
D-
USB0_
D_N
USB0_DATA0...7

FTDI, U17


D+
USB0_
D_P
USB0_DATA0...7MIO 52...63 FPGA Bank 502
FTDI, U17
VbusUSB_VBUSGND



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USB3.0 PinSchematicConnected toNotes
D-USB0_D_NUSB PHY, U22
D+USB0_D_PUSB PHY, U22
StdA_
StdA_
SSRX-USB_RX2_N
-
FPGA Bank 505
StdA_SSRX+USB_RX2_P
-
FPGA Bank 505
StdA_SSTX-
U3D2_N
USB_TX2_NFPGA Bank 505
StdA_SSTX+
U3D2_P
USB_TX2_PFPGA Bank 505
VBUSVBUSUSB PHY, U22