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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables


      • Scroll Title
        anchorTable_tablename
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefaultstyle
        widthssortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.


Scroll pdf ignore

Table of Contents

Table of Contents

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The Trenz Electronic TE0802 is an evalution modulea development board integrating a Xilinx Zynq UltraScale+ . Other assembly options for the FPGA and the memory chips are available. Please contact us for further information.

Refer to http://trenz.org/te0802-info for the current online version of this manual and other available documentation.

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Notes :

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Note:
 'Key Features' description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

  • MPSoC: Xilinx Zynq   XCZU2CG -1SBVA484E
  • SDRAM: LPDDR4-3733 8Gb 256Mx32 
  •  Xilinx Zynq UltraScale+ MPSoC
    • Package: 1SBVA484E
    • Speed Grade: -1 (Slowest)

    • Temperature Grade: Extended (0 to +100 °C)

  • RAM/Storages:
    • SDRAM: LPDDR4 8Gb 256Mx16x 2 
    • SPI Flash 
    Storages:
    • SPI Flash 256Mb (32M x 8) 133 MHz
    • EEPROMs 2Kb (256 x 8)
    • EEPROMs 4Kb (512 x 8)
  • Interfaces: 
    • USB JTAG/UART microUSB
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
    • microSD Card
    • M.2 SSD PCIe
    • 3.5 mm Earphone Jack (PWM Output)
    • Display
    Interfaces: 
    • Port
    • DisplayPort
    • VGA
    • 4 Digit 7-Segment LED Display
    • 8 LEDs
  • Audio:
    • 3.5 mm Jack (PWM Output)
    • 5 User Buttons
    • 8 Bit
    Input:
    • 5 User Buttons
    • 8 Bit Slide Switches
    • Reset Button
    User I/O:
    • 2x Pmod Connector
    Communication:
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
    Debug
    • USB JTAG/UART microUSB
  • Power
    • 5 V +/- 10%
    • ~3.5 W
  • Dimension: 100mm x 100mm

Block Diagram

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add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
anchorFigure_OV_BD
titleTE0802 Block Diagram


Scroll Ignore

draw.io Diagram
bordertruefalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision4
diagramNameTE08202-02TE0802_OV_BD
simpleViewerfalse
width
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diagramWidthtbstyle611hidden
revisiondiagramWidth14638



Scroll Only

Image RemovedImage Added


Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
anchorFigure_OV_MC
titleTE0802 Main Components (Picture shows Revision 01)


Scroll Ignore

draw.io Diagram
bordertruefalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision10
diagramNameTE0802_diagramNameTE0802_OV_MC
simpleViewerfalsetrue
width
diagramWidth602
linksauto
tbstylehidden
diagramWidth640revision8


Scroll Only


  1. Xilinx Zynq UltraScale+ MPSoc, U14
  2. LPDDR4 SDRAM, U13
  3. M.2 Key M PCIe x1, U5
  4. SPI Flash Memory, U16
  5. EEPROM, U2, U18
  6. Oscillator, U15, U7, U19, U23, U43
  7. Clock Generator, U8
  8. Clock Generator Programming Connector, J14
  9. Grove Connector, J10
  10. Pmod Host Socket, J5...6
  11. Headphone Jack, J12
  12. D-Sub Connector, J7
  13. DisplayPort, J3
  14. RJ45 Socket, J4
  15. Ethernet PHY, U6
  16. USB Type A, J11
  17. USB 2.0 PHY, U22
  18. Micro USB 2.0 Type B, J8
  19. FTDI USB 2.0 to JTAG/UART Converter, U17
  20. microSD Card, J9
  21. Slide Switch, S1
  22. Push Button, BTN1...5
  23. DIP Switch, S7...8
  24. 4 Digit 7-Segment LED Display, D9
  25. 8x LEDs (Red), LED0...7
  26. Power Jack, J13
  27. Overvoltage/Undervoltage/Reverse Supply Protector, U12
  28. Power Management Integrated Circuit (PMIC), U1, U9
  29. Power Good LED (Green), D12

...

Scroll Title
anchorTable_OV_IDS
titleInitial Delivery State of Programmable Devices on the Module

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Storage device name

Content

Notes

SPI Flash (U16)

Not programmed


EEPROM (U2)Not programmedExcept Ethernet MAC
EEPROM (U18)Programmed

FTDI Configuration

LPDDR4 SDRAM (U13)Not programmed


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

Bootmode signals must be set through DIP Switch S1. 

QSPI(24b)
Scroll Title
anchorTable_OV_BP
titleBoot process.Process

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MODE Signal State

MODE1

S1-2(B)

MODE0

MODE1

S1-1(A)

Boot Mode

MODE[

1

2:0]=000

0
OFF
0
OFF

JTAG

MODE[

1

2:0]=001

0
OFF
1
ONnot supported

MODE[

1

2:0]=010

1
ON
0
OFFQSPI(32 bit)

MODE[

1

2:0]=011

1
ON
1
ONSD0(2.0)


Reset setting is available through Push Button BTN6.

Scroll Title
anchorTable_OV_RST
titleReset process.Process

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Signal

Connected toNote

POR_B

BTN6, Push ButtonConnected to nRESET


Signals, Interfaces and Pins

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Scroll Title
anchorTable_SIP_B2B
titleGeneral I/O to Pin Header and Connectors Information

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FPGA BankConnector I/O Signal CountVoltage LevelNotes
Bank 503
J8, (
Micro USB
)J9
, J8 (
Micro SD Card)
J4, (RJ45)Bank 505J11, (USB 3.0)2 Differential Pairs0.85 VU5, (SSD M.2)Bank 505J3, (Display Port Connector)
over FTDI)4 Single Ended3.3 VJTAG
Bank 500Micro USB, J8 (over FTDI)2 Single Ended3.3 VUART
Bank 500Micro SD Card, J97
2 Differential Pairs0.85 VBank 26J7, (D-Sub Host Socket)2
Single Ended3.3 V
Bank
65, 66,J7, (D-Sub Host Socket)
502ETH RJ45, J4 (over ETH PHY)14
12
Single Ended1.8 V
Bank
65J12
505,
Headphone
502USB 3
Single Ended1.8 VBank 500J10, (Grove Connector
.0, J11 (USB2 over USB PHY)2 Differential Pairs, 12 Single Ended
3.3 VBank 26J5 (Pmod Host Socket)8 Single Ended
-- / 1.8V

Bank 505, 501

SSD M.2, U5

2 Differential Pairs, 5 Single Ended

-- / 3.3 V


Bank 505, 501Display Port Connector, J32 Differential Pairs, 5 Single Ended--/ 3.3 V
Bank 26
J6 (Pmod
, 65, 66,D-Sub Host Socket (VGA), J7
8
14 Single Ended3.3
V

Micro USB 2.0 Connector

FTDI FT2232 (U17) can be accessed through micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.

Micro SD Card Connector

V / 1.8 V / 1.8 V
Bank 65Earphone, J123 Single Ended1.8 V
Bank 500Grove Connector, J102 Single Ended3.3 V
Bank 26Pmod Host Socket, J58 Single Ended3.3 V
Bank 26Pmod Host Socket, J6 8 Single Ended3.3 V


Micro SD Card

TE0802 TEI0802 is equipped with a micro SD card connector (J9).

Scroll Title
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titleDisplay Port Socket Micro SD Card Connector Information

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style
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
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sortEnabledfalse
cellHighlightingtrue

Corresponding Signals
SchematicConnected toNotes

RJ45 Connector

TEI0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connectors J4 is connected to Ethernet PHYs U6.

...

anchorTable_SIP_RJ45
titleRJ45 Connector Information
SD_DAT0

MIO 13, FPGA Bank 500


SD_DAT1MIO 14, FPGA Bank 500
SD_DAT2MIO 15, FPGA Bank 500
SD_DAT3MIO 16, FPGA Bank 500
SD_CLKMIO 22, FPGA Bank 500
SD_CMDMIO 21, FPGA Bank 500
SD_CDMIO 24, FPGA Bank 500


RJ45 Connector

TE0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connector J4 is connected to Ethernet PHYs U6

...

USB Connector

TEI0802 is equipped with a USB connector (J11).

Connected to
Scroll Title
anchorTable_SIP_VGARJ45
titleUSB Socket RJ45 Connector Information

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sortDirectionASC
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PinSchematic
Corresponding Signals
ETH PinNotes