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Scroll Title
anchorFigure_OV_BD
titleTE0802 Block Diagram


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Bootmode signals must be set through DIP Switch S9S1

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titleBoot Process

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MODE Signal State

MODE1

S1-2(B)

MODE0

S1-1(A)

Boot Mode

MODE[2:0]=000

OFFOFF

JTAG

MODE[2:0]=001

OFFONnot supported

MODE[2:0]=010

ONOFFQSPI(32 bit)

MODE[2:0]=011

ONONSD0(2.0)


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Scroll Title
anchorTable_OBP
titleOn-board Peripherals

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Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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Scroll Title
anchorTable_OBP_DIP_SWITCH
titleDIP Switches

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DesignatorSchematicConnected toFunctionalityNote
S1AS1-1(A)MODE0Pin J16, FPGA Bank 503DIPPulled-down to GND.
S1BS1-2(B)MODE1Pin H15, FPGA Bank 503DIPPulled-down to GND.
S1CS1-3(C)USER_CFG0Pin A4, FPGA Bank 66DIPPulled-down to GND.
S1DS1-4(D)USER_CFG1Pin B4, FPGA Bank 66DIPPulled-down to GND.
S7AS7-1(A)USER_SW7Pin M5, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7BS7-2(B)USER_SW6Pin M4, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7CS7-3(C)USER_SW5Pin J2, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7DS7-4(D)USER_SW4Pin K1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8AS8-1(A)USER_SW3Pin L1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8BS8-2(B)USER_SW2Pin M1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8CS8-3(C)USER_SW1Pin P2, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8DS8-4(D)USER_SW0Pin P3, FPGA Bank 65DIPPulled-up to +1.8V_PL.


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Scroll Title
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titleDocument Change History

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DateRevisionContributorDescription

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Technical Specifications updated
  • Typo correction
2020-11-19v.65Pedram Babakhani
  • initial release

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