Dip | Setting | Note |
---|
S1 |
| Push button configured by CPLD as reset |
S2-1 | OFF | The choice OFF, ON, OFF selects 1.8V FMC_VADJ, which is a valid bank power for TE0720.
|
S2-2 | OFFON |
S2-3 | OFF |
S2-4 | OFF | Selects 4x5 module SOC/FPGA JTAG |
S2-5 | OFF |
S2-6 | OFF |
S2-7 | ON | Module power enable. |
S2-8 | OFF | Extended power sequenzing (if implemented). |
S3-1 | OFF | For Zynq modules: Primary Boot Mode SD/QSPI. OFF corresponds to boot from SD card. |
S3-2 | OFF | Overide automatic enable FMC_VADJ. (1)(2) |