In this section you must explain how to power on the board and run the Reference Design (test board) on the particular module. The main points must be mentioned are:

  • Overview of the board (point out the LEDs, Ethernets, Switches and etc on the board overview)
  • Explain Switches functionality
  • Explain user LEDs

  • Explain the UART connection

  • Refer to the Reference Design

    For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .



Table of Contents

TEF1002

Overview




  1. 4x5 module connectors
  2. Jumper J4 (VCCIOA)
  3. Jumper J7 (VCCA_SD)
  4. Dip switches S2 and S3
  5. 6-pin PCIe ATX Power Connector
  6. micro USB  connector for FTDI USB to JTAG/UART bridge
  7. Reset push button
  8. Power LED
  9. Status LED
  10. microSD card cage

Power supply

The input power supply must be mentioned.

Single 12V power supply with minimum current capability of 3A is recommended to power on the board via the 6-pin PCIe ATX connector. 

DIP-Switches and Push Buttons

Explain all DIP switches functionality.

Select dip switch settings according to the attached 4x5 module and your needs. Compare setting with TRM of your module and table in TRM of TEF1002. Following a general configuration is shown.


DipSettingNote
S1
Push button configured by CPLD as reset

S2-1

OFF

The choice OFF, ON, OFF selects 1.8V FMC_VADJ, which is a valid bank power for TE0720.


S2-2ON
S2-3OFF
S2-4OFFSelects 4x5 module SOC/FPGA JTAG
S2-5OFF
S2-6OFF
S2-7ONModule  power enable.
S2-8OFFExtended power sequenzing (if implemented).
S3-1OFFFor Zynq modules: Primary Boot Mode SD/QSPI. OFF corresponds to boot from SD card.
S3-2OFFOveride automatic enable FMC_VADJ.  (1)(2)


(1) Set to ON for TE0720 because bank 34 has to be powered to start up. Therefore FMC VADJ has to be set to a valid value e.g. 1.8V (See S2-1 to S2-3).

(2) For TE0820 set to on to use CLK0 (VCCO 65). Therefore FMC VADJ has to be set to a valid value e.g. 1.8V (See S2-1 to S2-3).

Jumpers

Explain all Jumpers functionality and connection.

For Jumper J7 compare TRM of actually used 4x5 module. The voltage of the bank where the SDIO signals reside has to selected. J4 selects the module bank voltage VCCIOA. It has to be selected in accordance with IO voltage of signals connected to FFA and FFB. If both FFA and FFB are not used any setting is ok. Do not leave open (communication of 4x5 module with TEF1002 CPLD is only possible with availabe VCCIOA)!

JumperPower Rail3.3V1.8VRemark
J7VCCA_SD1-22-3Powers SDIO Levelshifter on 4x5 module side.
J4VCCIOA1-22-3Powers 4x5 bank, where FFA and FFB high speed signals are connected.


LEDs

Explain all user LEDs functionality and connections.

There are four LEDs on the board. Two of them are user LEDS not further described here. Compare corresponding table in TEF1002 TRM.

LEDConnected toFunctionNotes
D33V3INPowerON when 3.3V generated from 12V input is up
D4SC CPLD U11, Pin C2StatusSC CPLD firmware dependent, for further description see firmware description.


JTAG/UART

Explain JTAG or UART connection breifly.

JTAG (first FTDI port) and UART (second FTDI port) is available via MicroUSB. External JTAG Programmer is not needed.

Reference Designs

In this Section you must refer to the Reference Design (Test board) for the particular module.

For Example: TE0728 Reference Designs

Notes

In this Section you must refer to the Resources Page for the particular module.

For Example: TE0728 Resources