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Overview

The Trenz Electronic TEF1002-02 is a baseboard in PCIe x1 form factor. It is a carrier for Trenz Electronic 4 x 5 SoMs, refer to page 4 x 5 SoM Carriers for more information about the SoMs supported by this carrier.

It hosts a FPGA Mezzanine Card (FMC LPC), a SFP+, CRUVI HS, RJ45 Ethernet and SATA socket. A USB OTG port and a JTAG/IO bridge together with additional JTAG headers and a System Controller complete this development platform.

Refer to https://trenz.org/tef1002-info for current online available documentation.

Key Features

  • On Board
    • Programmer :
      • USB 2.0 to JTAG/UART/IO converter with programmer configuration
      • EEPROM for programmer configuration
      • Oscillator
    • LEDs green:
      • 2x status - power and connected modules
      • 2x user
    • 5 V Fan
  • Interface
    • JTAG and UART
    • Trenz 4 x 5 SoM 3x B2B connector (Samtec LSHM) socket
    • FMC LPC :
      • IO:     68x SE / 34x DIFF and 2x CLKs (DIFF)
      • MGT:   1x MGT (RX/TX) and 1x MGT CLKs
      • JTAG, I2C, presence detection and power good
      • Variable voltage for IO and supply
    • PCIe x1 slot
    • SATA
    • SFP+ connector
    • RJ45 magnetic jack ethernet with 2x status LEDs
    • MicroSD card socket
    • CRUVI HS for 24x SE / 12x DIFF
    • Micro USB 2.0 type B for JTAG, UART and IO
    • Micro USB 2.0 type B for USB OTG
    • 5x2 pin header 2.54 mm for JTAG and UART
    • 3x2 pin header 2.54 mm for SoM JTAG
    • Button for reset
    • 10x DIP switches for selecting of :
      • FMC Voltage selection
      • JTAG muxing
      • SoM power and boot mode
      • 1x user definable
    • Jumper for setting SoM bank and SDIO voltage
  • Power
    • Single Rail 12.0 V power supply via PCIe 6 pin plug
    • Supply protection - Over and under voltage, Reverse polarity
    • Single rail power supply possible
  • Dimension
    • 98.4 mm x 167.65 mm
    • PCIe x1 card form factor

Block Diagram


TEF1002 block diagram


Main Components

TEF1002 main components
  1. USB 2.0 to JTAG/UART/IO bridge, U4
  2. EEPROM for configuration, U6
  3. FMC LPC socket, J1
  4. 5 V Fan, M1
  5. PCIe x1 slot, J3
  6. SATA, J31
  7. SFP+ connector, J12
  8. RJ45 ethernet magnetic jack, J9
  9. MicroSD card socket, J8
  10. CRUVI HS, J11
  11. Micro USB 2.0 type B for JTAG, UART and IO, J10
  12. Micro USB 2.0 type B for USB OTG, J16
  13. 5x2 pin header 2.54 mm for JTAG and UART, J5
  14. 3x2 pin header 2.54 mm for SoM JTAG, J19
  15. Button for reset, S1
  16. 8x DIP switches, S2
  17. 2x DIP switches, S3
  18. Jumper for SoM bank voltage, J4
  19. Jumper for SDIO voltage, J7
  20. LED status power green, D3
  21. LED status connected modules green, D4
  22. LEDs 2x user green, D1, D2
  23. 3x pin header 2.54 mm for backup supply, J6
  24. PCIe 6 pin plug power supply, J15
  25. Trenz 4 x 5 SoM 3x B2B socket, JB1, JB2, JB3
  26. System Controller, U11

Initial Delivery State

Storage device name

Designator

Content

Notes

System Controller

U11

Firmware

For further information see TEF1002 CPLD Firmware / TEF1002 SC CPLD MAX10.

EEPROM

U6

Programmer configuration

Do not overwrite!

Initial delivery state of programmable devices


Signals, Interfaces and Pins

Connectors

Connector Type

Designator

Interface

IO count

Notes

B2B

JB3

MGT SATA

1x MGT (RX/TX)


SATA

J31

MGT SATA

1x MGT (RX/TX)


B2B

JB3

MGT PCIe x1

1x MGT (RX/TX)


B2B

JB3

MGT PCIe x1

1x MGT CLK


PCIe x1 slot

J3

MGT PCIe x1

1x MGT (RX/TX)


PCIe x1 slot

J3

MGT PCIe x1

1x MGT CLK


B2B

JB3

MGT SFP+

1x MGT (RX/TX)


SFP+

J12

MGT SFP+

1x MGT (RX/TX)


B2B

JB3

MGT FMC

1x MGT (RX/TX)


B2B

JB3

MGT FMC

1x MGT CLK


B2B

JB3

IO FMC

12x SE/ 6x DIFF


B2B

JB3

IO FMC CLK

2x DIFF


B2B

JB2

IO FMC

56x SE/ 28x DIFF


FMC LPC

J1

MGT FMC

1x MGT (RX/TX)


FMC LPC

J1

MGT FMC

1x MGT CLK


FMC LPC

J1

IO FMC

12x SE/ 6x DIFF


FMC LPC

J1

IO FMC CLK

2x DIFF


FMC LPC

J1

IO FMC

56x SE/ 28x DIFF


B2B

JB1

SDIO

6x SE


MicroSD card

J8

SDIO

6x SE


B2B

JB1

IO CRUVI

24x SE / 12x DIFF


CRUVI HS

J11

IO CRUVI

24x SE / 12x DIFF


B2B

J1

JTAG SC

4x SE


Pin header 2.54 mm

J19

JTAG SC

4x SE


B2B

JB1

ETH MDI

4x DIFF


RJ45

J9

ETH MDI

4x DIFF


B2B

JB1

UART

2x SE


Micro USB type B

J10

JTAG / UART / IO

1x DIFF


B2B

JB3

USB OTG

1x DIFF


Micro USB type B

J16

USB OTG

1x DIFF


Pin header 2.54 mm

J5

JTAG / UART / Reset

7x SE


Board connectors

Test Points

Test

Point

REV03

REV02

Signal


Notes

Top

Bottom

Signal

TP1


x

5V0


TP2


x

3V3_PER

Not used


TP3


x

DDR_PWR


TP4

x


3V3IN


TP5

x


PG_3V3FMC

Not used


TP6

x


VREF_JTAG


TP7

x


VCCIOA


TP8

x


U10.PG

Not used


TP9

x


M3.3VOUT


TP10

x


M1.8VOUT


TP11


x

PSBATT

FMC_VADJ


TP12

x


5V0

Not used


TP13

x


USR_DIFIO1_N

Not used


TP14

x


USR_DIFIO1_P

Not used


TP15

x


12V


TP16

x


VADJ_CRUVI

Not used


TP17


x

M3.3VOUT


TP18


x

FMC_VADJ


TP19

x


3V3FMC


TP20

x


VCCA_SD


TP21

x


3.3V_SD


TP22


x

3.3V_SD

Not used


TP23

x


FMC_VADJ

Not used


TP24

x


U9.PGOOD

Not used


TP25

x


3V3_PER


TP26

x


PG_VADJ_CRUVI

Not used


TP27


x

3V3FMC

Not used


TP28


x

VADJ_CRUVI

Not used


TP29


x

3V3IN

Not used


TP30

x


PSBATT

Not used


TP31


x

12V

Not used


TP32

x


12V_FAULTn

Not used


TP33

x


PG_FMC_VADJ

Not used


TP34


x

5V_FAN

Not used


TP35

x


5V_FAN

Not used


TP36


x

M1.8VOUT

Not used


TP37


x

VCCA_SD

Not used


Test points information


On-board Peripherals

Chip / Interface

Designator

Connected to

Notes

System Controller

U11

  • USB 2.0 bridge, U4
  • USB VBUS switch, U12
  • 5 V fan switch, U17
  • FMC LPC connector J1
  • PCIe x1, J3
  • SFP+, J12
  • CRUVI HS, J11
  • 5x2 pin header JTAG and UART, J5
  • LEDs RJ45 ethernet, J9B, J9C
  • LEDs D1, D2, D4
  • Button reset S1
  • DIP switches S2, S3
  • B2B JB1, JB2

For further information see TEF1002 CPLD Firmware / TEF1002 SC CPLD MAX10.

USB 2.0 bridge

U4

  • System Control U11
  • EEPROM Programmer Configuration U6
  • Oscillator U7
  • Micro USB type B J10
  • B2B JB1


EEPROM Programmer Configuration

U6

  • USB bridge U4

Do not overwrite!

Oscillator

U7

  • USB 2.0 bridge, U4

12 MHz

On-board peripherals


Configuration and System Control Signals

Control signals represent hardware defined logic states, for final state consider the firmware and reference designs.

Control Signals and Buses

Signal Name

Connector.Pin

Direction 1)

Description 2)

EN1

JB1.27

OUT

Enable SoM power.

PGOOD

JB1.29

IN

Power Good signal for monitoring SoM voltages.

MODE

JB1.31

OUT

SoM Boot Mode selection.

NOSEQ

JB1.8

OUT

Influence SoM System Controller power management.

VBUS_V_EN / USB-VBUS

JB3.54 / JB3.56

IN / OUT

USB OTG VBUS control signals.

RESIN

JB2.17

OUT

Reset signal to SoM.

M10_RST

J5.6

IN

Reset System Controller.

M_JTAGEN

JB1.90

OUT

Select SoM JTAG target.

UART ( UART_RX / UART_TX )

JB1.86 / JB1.91

Signal dependent

SoM UART.

JTAG ( M_TMS / M_TDI / M_TDO / M_TCK )

JB2.94 / JB2.96 / JB2.98 / JB2.100

Signal dependent

SoM JTAG.

JTAG ( TCK / TDO / TMS / TDI )

J5.1 / J5.3 / J5.5 / J5.9

Signal dependent

JTAG System Controller.

UART ( M10_TX / M10_RX )

J5.7 / J5.8

Signal dependent

UART System Controller.

JTAG ( PJTAG_TCK / PJTAG_TDO / PJTAG_TDI / PJTAG_TMS )

J19.1 / J19.2 / J19.3 / J19.4

Signal dependent

JTAG SoM.

1) Direction:

    • IN: Input from the point of view of this board.

    • OUT: Output from the point of view of this board.

    • INOUT: Bidirectional signal.
    • Signal dependent: A Signal can have different functions and directions as part of a Bus.

2) Refer to TEF1002 SC CPLD MAX10 for further information.

Control signals and buses

Jumpers

Jumper

header

Net name / Connector.pin


Notes

Output

Input

J4




M3.3VOUT / J4.1


Set voltage for SoM IO.


VCCIOA / J4.2



M1.8VOUT / J4.3

J7




M3.3VOUT / J7.1


Set voltage for SDIO.


VCCA_SD / J7.2



M1.8VOUT / J7.3

Jumpers

Buttons

Button


Signal


Voltage level

Function


Low

high

S1

BUTTON

pressed

unpressed

Manual reset signal for SoM.

Buttons

DIP switches

DIP switch group

DIP switch

Signal name / Connector.pin

Description








S2

S2A

VID0 / S2.1


Set voltage FMC_VADJ, refer to TEF1002 CPLD Firmware - FMC VADJ Power for further information.


S2B

VID1 / S2.2

S2C

VID2 / S2.3

S2D

JTAGEN / S2.4


Muxing of JTAG signals, refer to TEF1002 CPLD Firmware - JTAG MUX for further information.


S2E

M_JTAGEN / S2.5

S2F

FMC_JTAG / S2.6

S2G

CM0 / S2.7


Set SoM control signals, refer to TEF1002 CPLD Firmware - Module control for further information.


S2H

CM1 / S2.8


S3

S3A

CM2 / S3.A

S3B

USR0 / S3.B

User definable signal

DIP switches

Power and Power-On Sequence

Power Rails


Power Rail Name / Schematic Name

Connector.Pin

Description

Notes

12V_input_A

J15.1 / J15.2 / J15.3

Carrier supply via PCIe 6 pin connector.


M3.3VOUT

JB2.9 / JB2.11

Auxiliary IO supply input from SoM.


M3.3VOUT

J1E.D32 / J4.1 / J7.1

Auxiliary IO Supply output from SoM.


M3.3VOUT

J19.6

Supply for external IO/JTAG device.


M1.8VOUT

J4.3 / J7.3

Auxiliary IO Supply output from SoM.


PSBATT

J6.2

Backup supply input.

SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs .

M1.8VOUT

JB1.40

Auxiliary IO Supply from SoM.

SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs .

VREF_JTAG

JB2.92

JTAG IO voltage.

SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs .

DDR_PWR

JB2.20

SoM DDR voltage reference.

SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs .

5V0

JB1.2 / JB1.4 / JB1.6 / JB2.1 / JB2.3 / JB2.5 / JB2.7

SoM supply


VCCIOA

JB1.10 / JB1.12

SoM IO bank supply


PSBATT

JB1.80

SoM backup supply


FMC_VADJ

JB2.2 / JB2.4 / JB2.6 / JB2.8 / JB2.10 /

J1E.G39 / J1E.H40

SoM FMC voltage supply.


3V3IN

JB1.14 / JB1.16

J5.4

JTAG IO voltage reference.


1) Direction:

    • IN: Input from the point of view of this board.
    • OUT: Output from the point of view of this board.
Power rails

Recommended Power up Sequencing

Sequence

Net name

Recommended Voltage Range

Pull-up/down

Description

Notes

0

-

-

-

Configuration SoM signal setup.

See Configuration and System Control Signals.

1

VIN

11.4 V to 12.6 V

-

Apply Main Carrier supply.


Power sequencing

Board to Board Connectors

These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.

4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.

  • 2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
  • 1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)
Connector Mating height

When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height

Order numberConnector on baseboardcompatible toMating height
23836REF-189016-01LSHM-150-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-150-03.0-L-DV-A-S-K-TRLSHM-150-03.0-L-DV-A-S-K-TR7.0 mm
23838REF-189016-02LSHM-150-04.0-L-DV-A-S-K-TR8.0 mm

LSHM-150-06.0-L-DV-A-S-K-TRLSHM-150-06.0-L-DV-A-S-K-TR10.0mm
26125REF-189017-01LSHM-130-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-130-03.0-L-DV-A-S-K-TRLSHM-130-03.0-L-DV-A-S-K-TR7.0 mm
24903 REF-189017-02LSHM-130-04.0-L-DV-A-S-K-TR8.0 mm

LSHM-130-06.0-L-DV-A-S-K-TRLSHM-130-06.0-L-DV-A-S-K-TR10.0mm
Connectors.

The module can be manufactured using other connectors upon request.

Connector Speed Ratings

The LSHM connector speed rating depends on the stacking height; please see the following table:

Stacking heightSpeed rating
12 mm, Single-Ended7.5 GHz / 15 Gbps
12 mm, Differential

6.5 GHz / 13 Gbps

5 mm, Single-Ended11.5 GHz / 23 Gbps
5 mm, Differential7.0 GHz / 14 Gbps
Speed rating.
Current Rating

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Connector Mechanical Ratings
  • Shock: 100G, 6 ms Sine
  • Vibration: 7.5G random, 2 hours per axis, 3 axes total


Manufacturer Documentation

  File Modified
PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report Apr 07, 2016 by Thorsten Trenz
PDF File lshm_dv.pdf LSHM catalog page Apr 07, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing Apr 07, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing Apr 07, 2016 by Thorsten Trenz
PDF File REF-189016-01.pdf Technical Drawing Apr 07, 2016 by Thorsten Trenz
PDF File REF-189016-02.pdf Technical Drawing Apr 07, 2016 by Thorsten Trenz
PDF File REF-189017-01.pdf Technical Drawing Apr 07, 2016 by Thorsten Trenz
PDF File REF-189017-02.pdf Technical Drawing Apr 07, 2016 by Thorsten Trenz
PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report Apr 07, 2016 by Thorsten Trenz
PDF File tc0929--2611_qua(1).pdf Shock and vibration report Apr 07, 2016 by Thorsten Trenz



Technical Specifications

Absolute Maximum Ratings *)

Warning!

The listed values ONLY reflect this board. Connected Carriers / SoMs / Boards are not considered. 

Power Rail Name / Schematic Name

Description

Min

Max

Unit

Notes

12V_input_A

Carrier supply via PCIe 6 pin connector.

-25

+25

V


M3.3VOUT

Auxiliary IO Supply from SoM.

-0.3

6.3

V


M1.8VOUT

Auxiliary IO Supply from SoM.

-

-

V

SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs .

VREF_JTAG

JTAG IO voltage.

-0.5

3.9

V

SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs .

PSBATT

Backup supply input

-

-

V

SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs .

DDR_PWR

SoM DDR voltage reference.

-

-

V

SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs .

Absolute maximum ratings

*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Temperature range

Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.

The categories are:

  • Modules with commercial (C) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 70 °C.
  • Modules with extended (E) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 85 °C.
  • Modules with industrial (I) temperature grade are equipped with components that cover at least the ambient temperature range of -40 °C to 85 °C.

These categories do not take into account the entire custom system consisting of:

  • Customer SoC/FPGA design. The allowed main SoC/FPGA temperature range is specified from the vendor by junction temperature using corresponding classes (C, E, I). See vendor documentation.
  • Cooling solution, active and or passive cooling.
  • Climate or environmental conditions besides ambient temperature range.
  • Module orientation, neighbouring assemblies, neither other heat sources nor the SoC as heat source to other components.

The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.

Voltage rails

The following table aims to be generic for all variants. The voltage ranges are consistent across assembly variants, but exceptions are possible (custom request).

Parameter

Min

Max

Units

Reference Document

12V_input_A

11.4

12.6

V

Schematic

M3.3VOUT

3.201

3.399

V

Schematic

M1.8VOUT

1.746

1.854

V

SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs .

VREF_JTAG

1.0

3.465

V

MAX10 FPGA datasheet.

SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs .

PSBATT

-

-

V

SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs .

DDR_PWR

-

-

V

SoM dependent, refer to 4 x 5 SoM Carriers - Supported SoMs .

Recommended operating conditions

Physical Dimensions

  • Module size: 98.4 mm x 167.65 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8.0 mm.

  • PCB thickness: 1.714 mm ±10 %.

Physical dimension

Currently Offered Variants 

Trenz shop TEF1002 overview page
English pageGerman page
Trenz Electronic shop overview

Revision History

Hardware Revision History

The hardware revision number can be found on the PCB board together with the module's model number, separated by a dash.

Board hardware revision number

Date

Revision

Changes

Documentation Link

2025-09

03

  1. S/N1 serial number component removed.
  2. ESD , UKCA , RoHS logo added.
  3. PM1 - PM6 changed from FIDU-DOT-small to FIDU-DOT-mini.
  4. L6 , L7 changed from 1uH to 4.7uH, C37 changed from 100n to 10u, C38 and C41 changed from 10uF 16V 0805 to 22uF 10V 0603 according SFP+ filter specification recomendations.
  5. U7 SiT8008AI-73-XXS-12.000000E (NRND) changed to SiT8008BI-73-XXS-12.000000E.
  6. Q1,Q3,Q4 TPS27081ADDCR changed to U17 , U18 , U16 MP5077GG-Z.
  7. C9 , C10 100nF 25V changed to 220nF 16V. AMD UG583 recommends 176-265nF for PS-GTR PCIe TX.
  8. C11 , C12 100nF X5R 25V 0402 changed to 10nF X7R 16V. AMD UG583 recommends 10nF for PS-GTR PCIe CLK.
  9. All SCH and PCB components updated from library.
  10. T1 , T2 SIS444DN-T1-GE3 (EOL) changed to Si7114ADN-T1-GE3.
  11. U1 EN5335QI (EOL) changed to MIC24046YFL and changed net names accordingly: VID2_FMC_VADJ -> VID0_FMC_DIR, FFB_SDA -> VID1_FMC_DIR 12) U9 LTM4638EY#PBF changed to MPQ8633BGLE-Z.
  12. U10 , U14 EN6338QI (obsolete) changed to MPM3834CGPA-Z.
  13. Change connections for pins:
  • pin U13:2 was connected to net OTG-D_P , now connected to net O2-D_P
  • pin U13:3 was connected to net OTG-D_N , now connected to net O2-D_N
  • pin U5:2 was connected to net D_P , now connected to net USB_P
  • pin U5:3 was connected to net D_N , now connected to net USB_N
  1. FireFly J11, J13, J14, J18, SNAP2, SNAP3 changed to CRUVI HS J11 (cruvi.com).
  2. C73 , C80 0402 6.3V changed to 0603 10V.
  3. Legal Notices page added.
  4. U21 and R88 added for powering CRUVI VADJ.
  5. Power_Overview page updated.
  6. MISC1 Digilent Serialnumber removed. R89 added.
  7. VOUT coding table on page CPLD changed according U1 changes.
  8. System overview, supported voltage range table added at page TEF1002.SchDoc.
  9. C1 , C33 , C34 0805 X7R changed to 0402 X5R. C21 , C23 6.3V changed to 25V. R36 49R9 0402 changed to 33R 0201. R63 1k changed to 1k05. BOM optimization.
  10. R6 10k changed to 5.1k. New pull-down will be more reliable (MAX10 has default internal pull-up in the same range with old pull-down resistor).
  11. TP2 , TP5 , TP8 , TP12 , TP13 , TP14 , TP16 , TP22 , TP23 , TP26 - TP37 , R101 added.
  12. J9A TRJG4820G4NL changed to Würth 74991114411 with better EMI performance. R117, R118 added.

REV03
PCN

2019-12

02

  1. Replace SD-Card socket by a push/pull version, Added card detect on CPLD. Added series resistors.
  2. Replaced PJTAG header J19 by 2x3 pin header and removed 0Ohm series resistors.
  3. Added pulldown on M3.3OUT R76 and FMC_FAN_EN R75.
  4. Replaced J6 with 3pin header (GND, PSBATT, GND).
  5. Changed GTR lanes SATA<->PCIe (compability for TE0820).
  6. Removed TP 22 23 24, and replaced J5 by header for TEI0004.
  7. J5 JTAG directly connected to CPLD. FTDI JTAG moved to other pins.
  8. Inverted dips for JTAGEN and M_JTAG.
  9. Moved FMC and SFP.
  10. Moved FMC_JTAG and USR dip switches to other Bank.
  11. Changed USB power switch.
  12. Added SATA power switch with enable and overcurrent on CPLD for 7pin power configuration.
  13. Reworked 5V0 and 3V3IN power supply.
  14. Added optional R and C for slew rate adjustment of powerswitches Q1, Q3, Q4 (04.05.2022).
  15. Set S/N track-it pad not fitted (EOL)
  16. SFP Cage dessignator J17 changed to MP1
  17. J5 Parameter Mixed changed from Hand to SMT

REV02
PCN

2019-05

01

  • Initial development


Hardware revision history

Document Change History

DateRevisionContributorDescription

Kilian Jahn

  • Updated to TRM template 4.3.9

2025-10-20

v.35

Maksim Tserabei

  • Typo correction

  • Updated to  TEF1002-03
2020-01-29v.28Martin Rohrmüller
  • Updated to REV02
2019-09-06v.25Martin Rohrmüller
  • Initial version

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all

  • --
Document change history.

Disclaimer

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Trenz Electronic GmbH (“Manufacturer”) excludes any liability for inappropriate use in such contexts. The Customer bears all responsibility for verifying suitability and compliance with applicable regulations when deploying in any critical-use scenario. The Customer also agrees to indemnify and hold harmless the Manufacturer from any third-party claims or liabilities arising from such use.

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The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.

Environmental Protection

To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.

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REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.



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