Page History
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- Xilinx Zynq UltraScale+ MPSoc, U14
- Oscillator, U15, U7, U23, U19, U43
- Slide Switch, S1
- Headphone Jack, J12
- SPI Flash Memory, U16
- EEPROM, U2, U18
- LPDDR4 SDRAM, U13
- DisplayPort, J3
- M.2 Key M PCIe x1, U5
- Ethernet PHY, U6
- RJ45 Socket, J4
- Grove Connector, J10
- Pmod Host Socket, J5...6
- D-Sub Connector, J7
- DIP Switch, S7...8
- Push Button, BTN1...5
- USB Type A, J11
- USB 2.0 PHY, U22
- microSD Card, J9
- FTDI USB 2.0 to JTAG/UART Converter, U17
- Micro USB 2.0 Type B, J8
- Clock Generator, U8
- Clock Generator Programming Connector, J14
- 4 Digit 7-Segment LED Display, D9
- 8x LEDs (Red), LED0...7
- Power Jack, J13
- Overvoltage/Undervoltage/Reverse Supply Protector, U12
- Power Management Integrated Circuit (PMIC), U1, U9
- Power Good LED (Green), D12
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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