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  • MPSoC: Xilinx Zynq XCZU2CG-1SBVA484E
  • SDRAM: LPDDR4-3733 8Gb 256Mx32 
  • Storages:
    • SPI Flash 256Mb (32M x 8) 133MHz
    • microSD Card
    • M.2 SSD PCIe
  • Display Interfaces: 
    • DisplayPort
    • VGA
    • 4 Digit 7-Segment LED Display
    • 8 LEDs
  • Audio:
    • 3.5mm Jack (PWM Output)
  • Input:
    • 5 User Buttons
    • 8 Bit Slide Switches
    • Reset Button
  • User I/O:
    • 2x Pmod Connector
  • Communication:
    • 1GB Ethernet RJ45
    • USB Host 3.0 Host (Type A Connector)
  • Debug
    • USB JTAG/UART microUSB
  • Power
    • 5V 5 V +/- 10%
    • ~3.5W5 W

Block Diagram

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add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
anchorFigure_OV_MC
titleTExxxx main componentsTE0802 Main Components (Picture shows Revision 01)


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draw.io Diagram
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  1. Xilinx Zynq UltraScale+ MPSoc, U14
  2. LPDDR4 SDRAM, U13
  3. M.2 Key M PCIe x1, U5
  4. SPI Flash Memory, U16
  5. EEPROM, U2, U18
  6. Oscillator, U15, U7, U19, U23, U43
  7. Clock Generator, U8
  8. Clock Generator Programming Connector, J14
  9. Grove Connector, J10
  10. Pmod Host Socket, J5...6
  11. Headphone Jack, J12
  12. D-Sub Connector, J7
  13. DisplayPort, J3
  14. RJ45 Socket, J4
  15. Ethernet PHY, U6
  16. USB Type A, J11
  17. USB 2.0 PHY, U22
  18. Micro USB 2.0 Type B, J8
  19. FTDI USB 2.0 to JTAG/UART Converter, U17
  20. microSD Card, J9
  21. Slide Switch, S1
  22. Push Button, BTN1...5
  23. DIP Switch, S7...8
  24. 4 Digit 7-Segment LED Display, D9
  25. 8x LEDs (Red), LED0...7
  26. Power Jack, J13
  27. Overvoltage/Undervoltage/Reverse Supply Protector, U12
  28. Power Management Integrated Circuit (PMIC), U1, U9
  29. Power Good LED (Green), D12

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Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices Delivery State of Programmable Devices on the moduleModule

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Storage device name

Content

Notes

Quad SPI Flash (U16)

Not programmed


EEPROM (U2)Not programmedExcept Ethernet MAC
EEPROM (U18)Programmed

FTDI Configuration

LPDDR4 SDRAM (U13)Not programmedDDR3 SDRAMSystem Controller CPLD


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

JTAG Interface

JTAG access to the TExxxx SoM through B2B connector JMX.FPGA bank number and number of I/O signals connected to the B2B connector:

Scroll Title
anchorTable_SIP_B2BJTG
titleGeneral PL I/O to B2B connectors informationJTAG pins connection

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FPGA Bank

JTAG Signal

B2B Connector

I/O Signal CountVoltage LevelNotes

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JTAG access to the TExxxx SoM through B2B connector JMX.

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anchorTable_SIP_JTG
titleJTAG pins connection
TMS
TDI
TDO
TCK


JTAG_EN


MIO Pins

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you must fill the table below with group of

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JTAG Signal

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B2B Connector

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MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI


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Power supply with minimum current capability of xx 3 A for system startup is recommended.

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Scroll Title
anchorFigure_PWR_PD
titlePower Distribution


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draw.io Diagram
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Power-On Sequence

Scroll Title
anchorFigure_PWR_PS
titlePower Sequency


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Power Rails

Scroll Title
anchorFigureTable_PWR_VMCPR
titleVoltage Monitor CircuitModule power rails.

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Power Rails

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anchorTable_PWR_PR
titleModule power rails.

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Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

























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Scroll Title
anchorTable_PWR_BV
titleZynq SoC bank voltages.

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Bank          

Schematic Name

Voltage

Notes

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Bank 503+3.3V3.3 V
Bank 26+3.3V3.3 V
Bank 65+1.8V_PL1.8 V
Bank 500+3.3V3.3 V
Bank 501+3.3V3.3 V
Bank 502+1.8V_PS1.8 V


Bank 504+1.1V_LPDDR41.1 V


Bank 505

+0.85V_MGTRAVCC

+1.8V_MGTRAVTT

0.85 V

1.8 V

???


use "include page" macro and link to the general B2B connector page of the module series,

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? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

  • 3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)

    Operating Temperature: -??°C ~ ??°C
    Current Rating: ??A per ContactNumber of Positions: ??
    Number of Rows: ??

Technical Specifications

Absolute Maximum Ratings

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anchorTable_TS_AMR
titlePS absolute maximum ratings

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SymbolsDescriptionMinMaxUnit
VINInput Supply Voltage (J13)45.5VVVVVVVV


Recommended Operating Conditions

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Scroll Title
anchorTable_TS_ROC
titleRecommended operating conditions.

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ParameterMinMaxUnitsReference DocumentVSee ???? datasheets.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.MaxUnitsReference Document
VIN45.5V


Physical Dimensions

Module size:

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100 mm ×

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100 mm.  Please download the assembly diagram for exact numbers.

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Mating height with standard connectors: ? mm.

PCB thickness: ?? 1,48 mm.

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
anchorTable_RH_DCH
titleDocument change history.

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DateRevisionContributorDescription

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dateFormatyyyy-MM-dd
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  • change listInitial Release

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all

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