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  • MPSoC: Xilinx Zynq XCZU2CG-1SBVA484E
  • SDRAM: LPDDR4-3733 8Gb 256Mx32 
  • Storages:
    • SPI Flash 256Mb (32M x 8) 133MHz 133 MHz
    • microSD Card
    • M.2 SSD PCIe
  • Display Interfaces: 
    • DisplayPort
    • VGA
    • 4 Digit 7-Segment LED Display
    • 8 LEDs
  • Audio:
    • 3.5mm 5 mm Jack (PWM Output)
  • Input:
    • 5 User Buttons
    • 8 Bit Slide Switches
    • Reset Button
  • User I/O:
    • 2x Pmod Connector
  • Communication:
    • 1GB Ethernet RJ45
    • USB 3.0 Host (Type A Connector)
  • Debug
    • USB JTAG/UART microUSB
  • Power
    • 5 V +/- 10%
    • ~3.5 W

...

Scroll Title
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titleTE0802 Block Diagram


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Main Components

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titleBoot process.

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MODE Signal State

MODE0MODE1Boot Mode

MODE[1:0]

00

JTAG

MODE[1:0]

01QSPI(24b)

MODE[1:0]

10QSPI(32)

MODE[1:0]

11SD0(2.0)




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titleReset process.

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Note

Signal

B2BI/OConnected toNote

POR_B

BTN6, Push ButtonConnected to nRESET


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

JTAG Interface

I/Os on Pin Headers and Connectors

FPGA bank number and number of I/O signals connected to the connectors:JTAG access to the TExxxx SoM through B2B connector JMX.

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titleJTAG pins connectionGeneral I/O to Pin Header and Connectors Information

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JTAG Signal

B2B Connector

TMSTDITDOTCKJTAG_EN

MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

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SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

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anchorTable_OBP_MIOs
titleMIOs pins

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchorTable_OBP
titleOn board peripherals

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Quad SPI Flash Memory

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Notes :

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FPGA BankConnector I/O Signal CountVoltage LevelNotes

J8, (Micro USB)



J9, (Micro SD Card)



J4, (RJ45)


Bank 505J11, (USB 3.0)2 Differential Pairs0.85 V

U5, (SSD M.2)


Bank 505J3, (Display Port Connector)2 Differential Pairs0.85 V
Bank 26J7, (D-Sub Host Socket)2 Single Ended3.3 V
Bank 65, 66,J7, (D-Sub Host Socket)12 Single Ended1.8 V
Bank 65J12, Headphone3 Single Ended1.8 V
Bank 500J10, (Grove Connector)2 Single Ended3.3 V
Bank 26J5 (Pmod Host Socket)8 Single Ended3.3 V
Bank 26J6 (Pmod Host Socket)8 Single Ended3.3 V


Pmod Host Socket

TEI0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.

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titlePmod SMD Host Socket Information

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DesignatorSignalsConnected to Notes
J5PMOD_A0...7Bank 26
J6PMOD_B0...7Bank 26


Micro USB 2.0 Connector

FTDI FT2232 (U17) can be accessed through micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.

RJ45 Connector

TEI0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connectors J4 is connected to Ethernet PHYs U6.

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titleRJ45 Connector Information

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PinSchematicETH PinNotes

































D-Sub Connector

TEI0802 is equipped with a D-Sub connector (J7).

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titleD-Sub Connector Information

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SchematicCorresponding SignalsConnected toNotes
VGA_REDVGA_R0...3Bank 65Red Channel
VGA_GREENVGA_G0...3Bank 65Green Channel
VGA_BLUEVGA_B0...3Bank 66Blue Channel
VGA_RGB_HSYNCVGA_HSBank 26Horizontal Sync
VGA_RGB_VSYNCVGA_VSBank 26Vertical Sync


Display Port Connector

TEI0802 is equipped with a Display Port connector (J3).

Scroll Title
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titleDisplay Port Socket Information

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SchematicCorresponding SignalsConnected toNotes
DP_TX_L0_P/NDP0_TX_P/NBank 505
DP_TX_L1_P/NDP1_TX_P/NBank 505
DP_TX_AUX_P/NDP_AUX_TX/RXBank 501


Headphone Connector

TEI0802 is equipped with a headphone connector (J12).

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titleHeadphone Connector Information

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SchematicCorresponding SignalsConnected toNotes













Micro SD Card Connector

TEI0802 is equipped with a micro SD card connector (J9).

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titleDisplay Port Socket Information

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SchematicCorresponding SignalsConnected toNotes













Grove Connector

TEI0802 is equipped with a grove connector (J10).

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titleGrove Connector Information

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SchematicCorresponding SignalsConnected toNotes













USB Connector

TEI0802 is equipped with a USB connector (J11).

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titleUSB Socket Information

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SchematicCorresponding SignalsConnected toNotes













SSD M.2 Connector

TEI0802 is equipped with a SSD M.2 connector (U5).

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titleSSD M.2 Connector Information

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SchematicCorresponding SignalsConnected toNotes














On-board Peripherals

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hiddentrue
idComments

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Scroll Title
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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
QSPI Flash MemoryU16
SDRAM MemoryU13
EEPROMU18, U2
USB PHYU22
Ethernet PHYU6
FTDI FT2232HU17
Clock GeneratorU8
OscillatorsU43, U19, U15, U7, U23
7-Segment LEDD9
User LEDs

Push Buttons

DIP SwitchS1
Switch


Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.


Scroll Title
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titleQuad SPI Interface MIOs and Pins

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MIO PinSchematicU16 PinNotes
MIO0MIO0B2SPI_CLK
MIO1MIO1D2SPI_DQ1
MIO2MIO2C4SPI_DQ2
MIO3MIO3D4SPI_DQ3
MIO4MIO4D3SPI_DQ0
MIO5MIO5C2SPI_CS


LPDDR4 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE0802 evaluation board has 1 GByte volatile LPDDR4 SDRAM IC for storing user application code and data. The details depends on the assembly option.

  • Part number:
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

EEPROM

Scroll Title
anchorTable_OBP_EEP
titleI2C EEPROM interface MIOs and pins

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MIO PinSchematicU?? PinNotes










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titleI2C Address for EEPROM

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MIO PinI2C AddressDesignatorNotes
MIO8...90x50U2


USB PHY

The TEI0802 is equipped with a USB PHY. 

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titleUSB PHY Connections and Pins

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USB PHY PinSignal Schematic NamesUSBNote

















































































Ethernet PHY

The TEI0802 is equipped with an Ethernet PHY (U6) which is connected to RJ45 (J) connector. 

Scroll Title
anchorTable_OBP_ETH
titleEthernet PHY Connections and Pins

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Ethernet PHY PinSignal Schematic NamesETHNote
TXD0...3
Bank
TXC
Bank
TXEN
Bank
RXD0...3
Bank
RXC/B-CAST_OFF
Bank
RXER/ISO
Bank
INTRP/nNAND_Tree
Bank
XI
Oscillator, U
MDC
Bank
MDIO
Bank
COL/CONFIG0
Bank
CRS/CONFIG1
Bank
RXDV/CONFIG2
Bank
LED0/NWAYEN

RJ45 - Green LED, J


LED1/SPEED

RJ45 - Yellow LED, J


nRST
Bank
RXM
RJ45, J
RXP
RJ45, J
TXM
RJ45, J
TXP
RJ45, J


FTDI FT2232

The FTDI chip U17 converts signals from USB 2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet for more information about the capacity of the FT2232H chip.
Channel A of FTDI FT2232H chip is used in MPPSE mode for JTAG. Channel B is used in UART mode.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U18.

Scroll Title
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titleFTDI Chip Interfaces and Pins

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FTDI Chip PinSignal Schematic NameConnected toNotes
ADBUS0TCKBankJTAG interface
ADBUS1TDIBank
ADBUS2TDOBank
ADBUS3TMS

Bank

BDBUS0FT_B_TXBankUART
BDBUS1FT_B_RXBankUART
EECSEECSEEPROM, U18
EECLKEECLKEEPROM, U18
EEDATAEEDATAEEPROM, U18
OSCI-12 MHz Oscillator, U19
DMD_NMicro USB 2.0, J8
DPD_PMicro USB 2.0, J8


Clock Generator

The TEI0802 is equipped with a clock generator (U8). 

Scroll Title
anchorTable_OBP_SPICLK_GEN
titleQuad SPI interface MIOs and pinsClock Generator Connections and Pins

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MIO
Clock Generator PinSignal Schematic Names
U?? PinNotes

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Note

















































































Oscillators

Notes

Scroll Title
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titleI2C interface MIOs and pinsOscillators

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MIO PinSchematicU? Pin

DesignatorDescriptionFrequencyNote
U43Clock for Clock Generator25 MHz
U15
33 MHz
U7
25 MHz
U23Clock for USB52 MHz


7-Segment Display

The TEI0802 has a 4-Digit-7-Segment LED display.

Scroll Title
anchorTable_OBP_I2C_RTC7SEG
titleI2C Address for RTC7-Segment LED Pins

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MIO
Pin
I2C Address
Schematic
Designator
Connected to Notes

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anchorTable_OBP_EEP
titleI2C EEPROM interface MIOs and pins
A/L1SEG_CA

B/L2SEG_CB

C/L3SEG_CC

DSEG_CD

ESEG_CE

FSEG_CF

GSEG_CG

DPSEG_CDP

A1SEG_AN

A2SEG_AN4

A3SEG_AN3

A4SEG_AN2

L1-L3SEG_AN1



User LEDs

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Scroll Title
anchorTable_OBP_I2C_EEPROMLED
titleI2C address for EEPROMOn-board LEDs

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MIO PinI2C AddressDesignatorNotes

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SchematicColorConnected toActive LevelNote
LED0...7RedBank 65High
D12GreenU9, PMICHigh


Push Buttons

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titleOn-board LEDsPush Buttons

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SchematicColorConnected toActive LevelNote

DDR3 SDRAM

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hiddentrue
idComments

Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

...

anchorTable_OBP_ETH
titleEthernet PHY to Zynq SoC connections

cellHighlightingtrue

SchematicDesignator Connected toFunctionalityNote
RESET
BankReset
RST_GPIO
BankReset/GPIO
USER_BTN_LEFT
BankUser Push Button
USER_BTN_UP
BankUser Push Button
USER_BTN_OK
BankUser Push Button
USER_BTN_RIGHT
BankUser Push Button
USER_BTN_DOWN
BankUser Push Button



DIP Switch

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CAN Transceiver

Scroll Title
anchorTable_OBP_CANDIP_SWITCH
titleCAN Tranciever interface MIOsDIP Switch

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Bank
Schematic
U?? PinNotesD-TxDriver InputR-RxReciever Output

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ColorConnected toActive LevelNote











Switch

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titleOsillatorsSwitch

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KHz
SchematicDesignatorColorDescriptionConnected toFrequencyActive LevelNoteMHzMHz












Power and Power-On Sequence

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