...
| Scroll Title |
|---|
| anchor | Table_SIP_B2B |
|---|
| title | General I/O to Pin Header and Connectors Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| FPGA Bank | Connector | I/O Signal Count | Voltage Level | Notes |
|---|
| Bank 503 | J8, (Micro USB) | 4 Single Ended | 3.3 V | JTAG | | Bank 500 | J8, (Micro USB) | 2 Single Ended | 3.3 V | UART | | Bank 500 | J9, (Micro SD Card) | 7 Single Ended | 3.3 V |
| | Bank 502 | J4, (RJ45) | 14 Single Ended | 1.8 V |
| | Bank 505 | J11, (USB 3.0) | 2 Differential Pairs | 0.85 V |
| Bank 505 | U5, (SSD M.2) | Bank 505 | J3, (Display Port Connector) | 2 Differential Pairs | 0.85 V |
| | Bank 26501 | J7U5, (D-Sub Host SocketSSD M.2) | 2 5 Single Ended | 3.3 V |
| | Bank 505 | J3, (Display Port Connector) | 2 Differential Pairs | 0.85 V |
| | Bank 26 | J7, (D-Sub Host Socket) | 2 Single Ended | 3.3 V |
| | Bank 65, 66, | J7, (D-Sub Host Socket) | 12 Single Ended | 1.8 V |
| | Bank 65 | J12, Headphone | 3 Single Ended | 1.8 V |
| | Bank 500 | J10, (Grove Connector) | 2 Single Ended | 3.3 V |
| | Bank 26 | J5 (Pmod Host Socket) | 8 Single Ended | 3.3 V |
| | Bank 26 | J6 (Pmod Host Socket) | 8 Single Ended | 3.3 V |
|
|
...
| Scroll Title |
|---|
| anchor | Table_SIP_VGA |
|---|
| title | Display Port Socket Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| SchematicCorresponding Signals | Connected to | Notes |
|---|
|
RJ45 Connector
TEI0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connectors J4 is connected to Ethernet PHYs U6.
...
| anchor | Table_SIP_RJ45 |
|---|
| title | RJ45 Connector Information |
|---|
| SD_DAT0 | MIO 13, FPGA Bank 500 |
| | SD_DAT1 | MIO 14, FPGA Bank 500 |
| | SD_DAT2 | MIO 15, FPGA Bank 500 |
| | SD_DAT3 | MIO 16, FPGA Bank 500 |
| | SD_CLK | MIO 22, FPGA Bank 500 |
| | SD_CMD | MIO 21, FPGA Bank 500 |
| | SD_CD | MIO 24, FPGA Bank 500 |
|
|
RJ45 Connector
TEI0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connectors J4 is connected to Ethernet PHYs U6
...
USB Connector
TEI0802 is equipped with a USB connector (J11).
| Scroll Title |
|---|
| anchor | Table_SIP_VGARJ45 |
|---|
| title | USB Socket RJ45 Connector Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Corresponding Signals | Connected to | |
...
...
TEI0802 is equipped with a SSD M.2 connector (U5).
...
| anchor | Table_SIP_VGA |
|---|
| title | SSD M.2 Connector Information |
|---|
| PHY_MDI0_P | MDIP[0] |
| | 3 | PHY_MDI0_N | MDIN[0] |
| | 4 | PHY_MDI1_P | MDIP[1] |
| | 5 | PHY_MDI1_N | MDIN[1] |
| | 6 | PHY_MDI2_P | MDIP[2] |
| | 7 | PHY_MDI2_N | MDIN[2] |
| | 8 | PHY_MDI3_P | MDIP[3] |
| | 9 | PHY_MDI3_N | MDIN[3] |
|
|
USB
...
Connector
TEI0802 is equipped with a Display Port USB connector (J3J11).
| Scroll Title |
|---|
| anchor | Table_SIP_VGA |
|---|
| title | Display Port USB Socket Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Pin | Schematic | Corresponding Signals | Connected to | Notes |
|---|
| D- |
DPTXL0_P/DP0_TX_P/N | Bank 505 | DP_TX_L1_P/N | DP1_TX_P/N | Bank 505 | DP_TX_AUX_P/N | DP_AUX_TX/RX | Bank 501 | |
...
| USB0_DATA0...7 | MIO 52...63 FPGA Bank 502 |
| | D+ | USB0_D_P | USB0_DATA0...7 | MIO 52...63 FPGA Bank 502 |
| | StdA_SSRX- | USB_RX2_N |
| FPGA Bank 505 |
| | StdA_SSRX+ | USB_RX2_P |
| FPGA Bank 505 |
| | StdA_SSTX- | U3D2_N | USB_TX2_N | FPGA Bank 505 |
| | StdA_SSTX+ | U3D2_P | USB_TX2_P | FPGA Bank 505 |
|
|
SSD M.2 Connector
TEI0802 is equipped with a D-Sub SSD M.2 connector (J7U5).
| Scroll Title |
|---|
| anchor | Table_SIP_VGA |
|---|
| title | D-Sub SSD M.2 Connector Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
Corresponding Signals| VGA_RED | VGA_R0...3 | Bank 65 | Red Channel | | VGA_GREEN | VGA_G0...3 | Bank 65 | Green Channel | | VGA_BLUE | VGA_B0...3 | Bank 66 | Blue Channel | | VGA_RGB_HSYNC | VGA_HS | Bank 26 | Horizontal Sync | | VGA_RGB_VSYNC | VGA_VS | Bank 26 | Vertical Sync | |
Headphone Connector
TEI0802 is equipped with a headphone connector (J12).
...
| anchor | Table_SIP_VGA |
|---|
| title | Headphone Connector Information |
|---|
|
|---|
| PERn0/SATA-B+ | SSD_RX3_N | Pin M22, FPGA Bank 505 |
| | PERp0/SATA-B- | SSD_RX3_P | Pin M21, FPGA Bank 505 |
| | PERn0/SATA-A+ | SSD_TXC3_N | Pin K22, FPGA Bank 505 |
| | PERp0/SATA-A- | SSD_TXC3_P | Pin M21, FPGA Bank 505 |
| | REFCLKN | SSD_RCLK_N | Pin 9, Clock Generator U8 |
| | REFCLKP | SSD_RCLK_P | Pin 10, Clock Generator U8 |
| | DAS/DSS# | SSD_DAS | MIO35, FPGA Bank 501 |
| | DEVSLP | SSD_SLEEP | MIO32, FPGA Bank 501 |
| | PERST# | SSD_PERSTn | MIO31, FPGA Bank 501 |
| | CLKREQ# | SSD_CLKRQ | MIO33, FPGA Bank 501 |
| | PEWake# | SSD_WAKE | MIO34, FPGA Bank 501 |
|
|
Display Port
...
Connector
TEI0802 is equipped with a grove Display Port connector (J10J3).
| Scroll Title |
|---|
| anchor | Table_SIP_VGA |
|---|
| title | Grove Connector Display Port Socket Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic | Corresponding Signals | Connected to | Notes |
|---|
|
Pmod Host Socket
TEI0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.
| DP_TX_L0_P/N | DP0_TX_P/N | Pin A19/A20, FPGA Bank 505 |
| | DP_TX_L1_P/N | DP1_TX_P/N | Pin C19/C20, FPGA Bank 505 |
| | DP_TX_AUX_P/N | DP_AUX_TX/RX | MIO27, MIO30, FPGA Bank 501 |
|
|
D-Sub Connector
TEI0802 is equipped with a D-Sub connector (J7).
| Scroll Title |
|---|
| anchor | Table_SIP_VGA |
|---|
| title | D-Sub Connector Information |
|---|
|
| Scroll Title |
|---|
| anchor | Table_SIP_SMD |
|---|
| title | Pmod SMD Host Socket Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
Designator| Schematic | Corresponding Signals | Connected |
|---|
to J5PMODA07 26J6 | PMOD_B0| 65 | Red Channel | | VGA_GREEN | VGA_G0... |
7 26 |
On-board Peripherals
| Page properties |
|---|
|
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
| Page properties |
|---|
|
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
| 65 | Green Channel | | VGA_BLUE | VGA_B0...3 | Bank 66 | Blue Channel | | VGA_RGB_HSYNC | VGA_HS | Bank 26 | Horizontal Sync | | VGA_RGB_VSYNC | VGA_VS | Bank 26 | Vertical Sync |
|
Headphone Connector
TEI0802 is equipped with a headphone connector (J12).
| Scroll Title |
|---|
| anchor | Table_OBPSIP_VGA |
|---|
| title | On board peripheralsHeadphone Connector Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
Quad SPI Flash Memory
...
Notes :
...
| JACKSNS | Pin F3, FPGA Bank 65 |
| | PWM_R | Pin F4, FPGA Bank 65 |
| | PWM_L | Pin E3, FPGA Bank 65 |
|
|
Grove Connector
TEI0802 is equipped with a grove connector (J10).
| Scroll Title |
|---|
| anchor | Table_SIP_VGA |
|---|
| title | Grove Connector Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic | Connected to | Notes |
|---|
| Grove_SCL0 | MIO18, FPGA Bank 500 |
| | Grove_SDA0 | MIO19, FPGA Bank 500 |
|
|
Pmod Host Socket
TEI0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.
| Scroll Title |
|---|
| anchor | Table_OBPSIP_SPISMD |
|---|
| title | Quad SPI Interface MIOs and PinsPmod SMD Host Socket Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
MIO PinSchematicU16 Pin| MIO0 | MIO0 | B2 | SPI_CLK | | MIO1 | MIO1 | D2 | SPI_DQ1 | | MIO2 | MIO2 | C4 | SPI_DQ2 | | MIO3 | MIO3 | D4 | SPI_DQ3 | | MIO4 | MIO4 | D3 | SPI_DQ0 | | MIO5 | MIO5 | C2 | SPI_CS | |
...
| J5 | PMOD_A0...7 | Bank 26 |
| | J6 | PMOD_B0...7 | Bank 26 |
|
|
On-board Peripherals
| Page properties |
|---|
|
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0802 evaluation board has 1 GByte volatile LPDDR4 SDRAM IC for storing user application code and data. The details depends on the assembly option.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
EEPROM
- add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
| Page properties |
|---|
|
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
| scrollscroll-title |
|---|
| anchor | Table_OBP_EEP |
|---|
| title | I2C EEPROM interface MIOs and pinsOn board peripherals |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
| Scroll Title |
|---|
| anchor | Table_OBP_I2C_EEPROM |
|---|
| title | I2C Address for EEPROM |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
| MIO Pin | I2C Address | Designator | Notes |
|---|
MIO8...9 | 0x50 | U2 |
USB PHY
...
Quad SPI Flash Memory
| Page properties |
|---|
|
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
| Scroll Title |
|---|
| anchor | Table_OBP_USBSPI |
|---|
| title | USB PHY Connections Quad SPI Interface MIOs and Pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
USB PHY | Signal Schematic Names | USB | Note | |
Ethernet PHY
| Schematic | U16 Pin | Notes |
|---|
| MIO0 | MIO0 | B2 | SPI_CLK | | MIO1 | MIO1 | D2 | SPI_DQ1 | | MIO2 | MIO2 | C4 | SPI_DQ2 | | MIO3 | MIO3 | D4 | SPI_DQ3 | | MIO4 | MIO4 | D3 | SPI_DQ0 | | MIO5 | MIO5 | C2 | SPI_CS |
|
LPDDR4 SDRAM
| Page properties |
|---|
|
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0802 evaluation board has 1 GByte volatile LPDDR4 SDRAM IC (U13) for storing user application code and data. The details depends on the assembly option.
- Part number:
- Supply voltage:
- Speed:
- NOR Flash
- Temperature:
EEPROM
| Scroll Title |
|---|
| anchor | Table_OBP_EEP |
|---|
| title | I2C EEPROM interface MIOs and pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| MIO Pin | Schematic | U2 Pin | Notes |
|---|
| MIO8 | Int_SCL1 | SCL |
| | MIO9 | Int_SDA1 | SDA |
|
|
| Scroll Title |
|---|
| anchor | Table_OBP_I2C_EEPROM |
|---|
| title | I2C Address for EEPROM |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| MIO Pin | I2C Address | Designator | Notes |
|---|
| MIO8...9 | 0x50 | U2 |
|
|
| Scroll Title |
|---|
| anchor | Table_OBP_EEP |
|---|
| title | I2C EEPROM interface MIOs and pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Pin | Schematic | U18 Pin | Notes |
|---|
| CS | EECS | 1 | FTDI | | CLK | EECLK | 2 | FTDI | | DIN/DO | EEDATA | 3/4 | FTDI |
|
USB ULPI PHY
The TEI0802 is equipped with a USB ULPI PHY.
| Scroll Title |
|---|
| anchor | Table_OBP_USB |
|---|
| title | USB ULPI PHY Connections and Pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| USB PHY Pin | Signal Schematic Names | Connected to | Note |
|---|
DATA0 | USB0_DATA0 | MIO56, FPGA Bank 502 |
| | DATA1 | USB0_DATA1 | MIO57, FPGA Bank 502 |
| | DATA2 | USB0_DATA2 | MIO54, FPGA Bank 502 |
| | DATA3 | USB0_DATA3 | MIO59, FPGA Bank 502 |
| | DATA4 | USB0_DATA4 | MIO60, FPGA Bank 502 |
| | DATA5 | USB0_DATA5 | MIO61, FPGA Bank 502 |
| | DATA6 | USB0_DATA6 | MIO62, FPGA Bank 502 |
| | DATA7 | USB0_DATA7 | MIO63, FPGA Bank 502 |
| | DIR | USB0_DIR | MIO53, FPGA Bank 502 |
| | NXT | USB0_NXP | MIO55, FPGA Bank 502 |
| | STP | USB0_STP | MIO58, FPGA Bank 502 |
| | RESETB | USB0_RST_N | MIO38, FPGA Bank 501 |
| | CPEN | USB0_VBUS_EN | Pin 1, U21 (Current-limited Power Switch) |
| | VBUS | VBUS | Pin 8, U21 (Current-limited Power Switch). Pin 1, J11 (USB Connector) |
| | ID | USB0_ID | Pulled-down to GND |
| | DP | USB0_D_P | Pin 3, J11 (USB Connector) |
| | DM | USB0_D_N | Pin 2, J11 (USB Connector) |
| | REFCLK | USB0_RCLK | Pin 3, U23 (Oscillator) |
| | CLKOUT | USB0_CLK | MIO52, FPGA Bank 502 |
|
|
Ethernet PHY
The TEI0802 is equipped with an Ethernet PHY (U6) which is connected to RJ45 (J) connector.
| Scroll Title |
|---|
| anchor | Table_OBP_ETH |
|---|
| title | Ethernet PHY Connections and Pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Ethernet PHY Pin | Signal Schematic Names | ETH | Note |
|---|
| TXD0 | ETH_TXD0 | MIO65, FPGA Bank 502 |
| | TXD1 | ETH_TXD1 | MIO66, FPGA Bank 502 |
| | TXD2 | ETH_TXD2 | MIO67, FPGA Bank 502 |
| | TXD3 | ETH_TXD3 | MIO68, FPGA Bank 502 |
| | TX_CTRL | ETH_TXCTL | MIO69, FPGA Bank 502 |
| | TX_CLK | ETH_CLK | MIO64, FPGA Bank 502 |
| | MDIO | ETH_MDIO | MIO77, FPGA Bank 502 | Pulled-up to +1.8V_PS | | MDC | ETH_MDC | MIO76, FPGA Bank 502 |
| | MDIP[0] | PHY_MDI0_P | Pin2, J4 (RJ45) |
| | MDIN[0] | PHY_MDI0_N | Pin3, J4 (RJ45) |
| | MDIP[1] | PHY_MDI1_P | Pin4, J4 (RJ45) |
| | MDIN[1] | PHY_MDI1_N | Pin5, J4 (RJ45) |
| | MDIP[2] | PHY_MDI2_P | Pin6, J4 (RJ45) |
| | MDIN[2] | PHY_MDI2_N | Pin7, J4 (RJ45) |
| | MDIP[3] | PHY_MDI3_P | Pin8, J4 (RJ45) |
| | MDIN[3] | PHY_MDI3_N | Pin9, J4 (RJ45) |
| | LED[0] | PHY_LED0 | LED, J4 (RJ45) |
| | LED[1] | PHY_LED1 | LED, J4 (RJ45) |
| | CONFIG | - | - | Pulled-up to +1.8V_PS | | XTAL_IN | ETH_XTAL_IN | Pin 3, U7 (Oscillator) |
| | RESETn | ETH_RST | MIO37, FPGA Bank 501 | Pulled-up to +1.8V_PS | | RX_CLK | ETH_RXCK | MIO70, FPGA Bank 502 |
| | RX_CTRL | ETH_RXCTL | MIO75, FPGA Bank 502 |
| | RXD[0] | ETH_RXD0 | MIO71, FPGA Bank 502 |
| | RXD[1] | ETH_RXD1 | MIO72, FPGA Bank 502 |
| | RXD[2] | ETH_RXD2 | MIO73, FPGA Bank 502 |
| | RXD[3] | ETH_RXD3 | MIO74, FPGA Bank 502 |
|
|
FTDI FT2232
The FTDI chip U17 converts signals from USB 2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet for more information about the capacity of the FT2232H chip.
Channel A of FTDI FT2232H chip is used in MPPSE mode for JTAG. Channel B is used in UART mode.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U18.The TEI0802 is equipped with an Ethernet PHY (U6) which is connected to RJ45 (J) connector.
| Scroll Title |
|---|
| anchor | Table_OBP_ETHFTDI |
|---|
| title | Ethernet PHY Connections FTDI Chip Interfaces and Pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
Ethernet PHY | FTDI Chip Pin | Signal Schematic |
|---|
NamesETHNote | TXD0...3 | Bank | TXC | Bank | TXEN | Bank | RXD0...3 | Bank | RXC/B-CAST_OFF | Bank | RXER/ISO | Bank | INTRP/nNAND_Tree | Bank | XI | Oscillator, U | MDC | Bank | MDIO | Bank | COL/CONFIG0 | Bank | CRS/CONFIG1 | Bank | RXDV/CONFIG2 | Bank | LED0/NWAYEN | RJ45 - Green LED, J | LED1/SPEED | RJ45 - Yellow LED, J | nRST | Bank | RXM | RJ45, J | RXP | RJ45, J | TXM | RJ45, J | TXP | RJ45, J | |
FTDI FT2232
The FTDI chip U17 converts signals from USB 2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet for more information about the capacity of the FT2232H chip.
Channel A of FTDI FT2232H chip is used in MPPSE mode for JTAG. Channel B is used in UART mode.
| Notes |
|---|
| ADBUS0 | TCK | Pin H13, FPGA Bank 503 | JTAG Interface | | ADBUS1 | TDI | Pin H12, FPGA Bank 503 | JTAG Interface | | ADBUS2 | TDO | Pin J13, FPGA Bank 503 | JTAG Interface | | ADBUS3 | TMS | Pin J12, FPGA Bank 503 | JTAG Interface | | BDBUS0 | FT_B_TX | MIO10, FPGA Bank 500 | UART | | BDBUS1 | FT_B_RX | MIO11, FPGA Bank 500 | UART | | EECS | EECS | Pin 1, U18 (EEPROM) |
| | EECLK | EECLK | Pin 2, U18 (EEPROM) |
| | EEDATA | EEDATA | Pin 3/4, U18 (EEPROM) |
| | OSCI | - | Pin 3, U19 (Oscillator) |
| | DM | D_N | Pin 2, J8 (Micro USB 2.0) |
| | DP | D_P | Pin 3, J8 (Micro USB 2.0) |
|
|
Clock Generator
The TEI0802 is equipped with a clock generator (U8). The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U18.
| Scroll Title |
|---|
| anchor | Table_OBP_CLK_FTDIGEN |
|---|
| title | FTDI Chip Interfaces Clock Generator Connections and Pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
FTDI Chip | Clock Generator Pin | Signal Schematic |
|---|
NameNotes| ADBUS0 | TCK | Bank | JTAG interface | | ADBUS1 | TDI | Bank | | ADBUS2 | TDO | Bank | | ADBUS3 | TMS | Bank | | BDBUS0 | FT_B_TX | Bank | UART | | BDBUS1 | FT_B_RX | Bank | UART | EECS | EECS | EEPROM, U18 | EECLK | EECLK | EEPROM, U18 | EEDATA | EEDATA | EEPROM, U18 | OSCI | - | 12 MHz Oscillator, U19 | DM | D_N | Micro USB 2.0, J8 | DP | D_P | Micro USB 2.0, J8 | |
Clock Generator
The TEI0802 is equipped with a clock generator (U8).
| REFP | - | Pin 3, U43 (Oscillator) |
| | REFSEL | REFSEL | - | Pulled-up to +3.3V | | RESETN/SYNC | CLK_GEN_RESET | Pin B5, FPGA Bank 26 | Pulled-up to +3.3V | | EEPROMSEL | EEPROMSEL | - | Pulled-up to +3.3V | | SDA/GPIO2 | CLK_GEN_SDA | - (Default), MIO9, FPGA Bank 500, Pin 2, J14 (Pin Header) | Pulled-up to +3.3V, (Default) Pulled-up to +3.3V, Pulled-up to +3.3V | | SCL/GPIO3 | CLK_GEN_SCL |
|
| | OE/GPIO4 | - |
|
| Y1P | CLK_Y1_P |
|
| | Y1N | CLK_Y1_N |
|
| Y2P | CLK_Y2_P |
|
| | Y2N | CLK_Y2_N |
|
| Y3P | CLK_Y3_P |
|
| | Y3N | CLK_Y3_N |
|
| Y4P | CLK_Y4_P |
|
| | Y4N | CLK_Y4_N |
|
| Scroll Title |
|---|
| anchor | Table_OBP_CLK_GEN |
|---|
| title | Clock Generator Connections and Pins |
|---|
|
| Scroll Table Layout |
|---|
|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
| Clock Generator Pin | Signal Schematic Names | Note |
|
|
|---|
Oscillators
| Scroll Title |
|---|
| anchor | Table_OBP_CLK |
|---|
| title | Oscillators |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Designator | Description | Frequency | Note |
|---|
| U43 | Clock for Clock Generator | 25 MHz |
| | U15 |
| 33 MHz |
| | U7 |
| 25 MHz |
| | U23 | Clock for USB | 52 MHz |
|
|
...