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Scroll Title
anchorTable_OBP
titleOn board peripherals

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S7, S8
Chip/InterfaceDesignatorNotes
QSPI Flash MemoryU16
SDRAM MemoryU13
EEPROMU2, U18
USB PHYU22
Ethernet PHYU6
FTDI FT2232HU17
Clock GeneratorU8
OscillatorsU7, U15, U19, U23, U43
7-Segment LEDD9
User LEDsLED0...7
Push ButtonsBTN1...5
DIP SwitchS1Switch, S7...8


Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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Scroll Title
anchorTable_OBP_CLK_GEN
titleClock Generator Connections and Pins

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Clock Generator PinSignal Schematic NamesConnected toNote
REFP-Pin 3, U43 (Oscillator)
REFSELREFSEL-Pulled-up to +3.3V
RESETN/SYNCCLK_GEN_RESETPin B5, FPGA Bank 26Pulled-up to +3.3V
EEPROMSELEEPROMSEL-Pulled-up to +3.3V
SDA/GPIO2CLK_GEN_SDA

- (Default),

MIO9, FPGA Bank 500 (R185/196 required),

Pin 2, J14 (Pin Header required)

Pulled-up to +3.3V, (Default)

Pulled-up to +3.3V,

Pulled-up to +3.3V

SCL/GPIO3CLK_GEN_SCL

- (Default),

MIO8, FPGA Bank 500 (R185/196 required),

Pin 3, J14 (Pin Header required)

Pulled-up to +3.3V, (Default)

Pulled-up to +3.3V,

Pulled-up to +3.3V

OE/GPIO4--Pulled-up to +3.3V

Y1P

CLK_Y1_P / CLK_DP_PPin G19, FPGA Bank 50527 MHz
Y1NCLK_Y1_N / CLK_DP_NPin G20, FPGA Bank 50527 MHzY1NCLK_Y1_N

Y2P

CLK_Y2_P / CLK_USB_PPin J19, FPGA Bank 50526 MHz
Y2NCLK_Y2_N / CLK_USB_NPin J20, FPGA Bank 50526 MHz

Y3P

CLK_Y3_P / CLK_PCIe_PPin L19, FPGA Bank 505100 MHz
Y3NCLK_Y3_N

Y4P

/ CLK_Y4_PY4NCLK_Y4_NPCIe_NPin L20, FPGA Bank 505100 MHz

Y4P

CLK_Y4_P / SSD_RCLK_PPin 55, U5 (M.2)100 MHz
Y4NCLK_Y4_N / SSD_RCLK_NPin 53, U5 (M.2)100 MHz


Oscillators

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titleOscillators

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U43 Clock Generator
DesignatorSignal Schematic NamesConnected toDescriptionFrequencyNote
U7ETH_XTAL_INPin 34, U6 (Ethernet PHY)Clock for Ethernet25 MHz
U1533 MHzU725 MHzPS_CLKPin H14, FPGA Bank 503Clock for FPGA33 MHz
U23USB_CLK / USB0_RCLKPin 26, U22 (USB PHY)U23Clock for USB52 MHz
U43-Pin 5, U8 (Clock Generator)Clock for Clock Generator25 MHz


7-Segment Display

The TEI0802 has a 4-Digit-7-Segment LED display.

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title7-Segment LED Pins

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PinSchematicConnected to Notes
A/L1CA / SEG_CAPin E4, FPGA Bank 65
B/L2CB / SEG_CBPin D3, FPGA Bank 65
C/L3CC / SEG_CCPin N5, FPGA Bank 65
DCD / SEG_CDPin P5, FPGA Bank 65
ECE / SEG_CE
F
Pin N4, FPGA Bank 65
FCF / SEG_CFPin C3, FPGA Bank 65
GCG / SEG_CGPin R5, FPGA Bank 65
DPCDP / SEG_CDPPin N3, FPGA Bank 65
A1SEG_
AN
AN1Pin A9, FPGA Bank 26
A2SEG_
AN4
AN2Pin B9, FPGA Bank 26
A3SEG_AN3Pin A7, FPGA Bank 26
A4SEG_
AN2
AN4Pin B6, FPGA Bank 26
L1-L3SEG_
AN1
ANPin A8, FPGA Bank 26



User LEDs

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titleOn-board LEDs

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SchematicColorConnected toActive LevelNote
LED0...7RedBank 65High
D12GreenU9, PMICHigh


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Scroll Title
anchorTable_OBP_PBTN
titleOn-board Push Buttons

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Designator SchematicDesignator Connected toFunctionalityNote
BTN_1USER_BTN_UPPin U2, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_2RESETBankResetRST_GPIOBankReset/GPIOUSER_BTN_LEFTPin R1, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_3USER_BTN_UPBankUser Push ButtonUSER_BTN_OKPin T1, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_4USER_BTN_RIGHTPin U1, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_5USER_BTN_DOWNBankPin T2, FPGA Bank 65User Push ButtonPulled-up to +1.8V_PL.
BTN_6POR_B

Pin 38, U1 (PMIC),

Pin 38, U9 (PMIC),

Pin K12, FPGA Bank 503

Reset ButtonPulled-up to +3.3V.



DIP Switch

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titleDIP Switch S1

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DesignatorSchematicColorConnected toActive LevelFunctionalityNote

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S1A
Scroll Title
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titleSwitch
MODE0Pin J16, FPGA Bank 503DIPPulled-down to GND.
S1BMODE1Pin H15, FPGA Bank 503DIPPulled-down to GND.
S1CUSER_CFG0Pin A4, FPGA Bank 66DIPPulled-down to GND.
S1DUSER_CFG1Pin B4, FPGA Bank 66DIPPulled-down to GND.
S7AUSER_SW7Pin M5, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7BUSER_SW6Pin M4, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7CUSER_SW5Pin J2, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S7DUSER_SW4Pin K1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8AUSER_SW3Pin L1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8BUSER_SW2Pin M1, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8CUSER_SW1Pin P2, FPGA Bank 65DIPPulled-up to +1.8V_PL.
S8DUSER_SW0Pin P3, FPGA Bank 65DIPPulled-up to +1.8V_PL.
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Note
SchematicColorConnected toActive Level


Power and Power-On Sequence

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