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The Trenz Electronic TE0802 is an evalution module. Other assymbly options for the FPGA and the memory chips are available. Please ask for further information.
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| Scroll Title |
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| anchor | Table_SIP_VGA |
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| title | USB Socket Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pin | Schematic | Corresponding Signals | Connected to | Notes |
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| D- | USB0_D_N | USB0_DATA0...7 | MIO 52...63 FPGA Bank 502 |
| | D+ | USB0_D_P | USB0_DATA0...7 | MIO 52...63 FPGA Bank 502 |
| | StdA_SSRX- | USB_RX2_N | - | FPGA Bank 505 |
| | StdA_SSRX+ | USB_RX2_P | - | FPGA Bank 505 |
| | StdA_SSTX- | U3D2_N | USB_TX2_N | FPGA Bank 505 |
| | StdA_SSTX+ | U3D2_P | USB_TX2_P | FPGA Bank 505 |
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| Scroll Title |
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY Connections and Pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Ethernet PHY Pin | Signal Schematic Names | ETH | Note |
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| TXD0 | ETH_TXD0 | MIO65, FPGA Bank 502 |
| | TXD1 | ETH_TXD1 | MIO66, FPGA Bank 502 |
| | TXD2 | ETH_TXD2 | MIO67, FPGA Bank 502 |
| | TXD3 | ETH_TXD3 | MIO68, FPGA Bank 502 |
| | TX_CTRL | ETH_TXCTL | MIO69, FPGA Bank 502 |
| | TX_CLK | ETH_CLK | MIO64, FPGA Bank 502 |
| | MDIO | ETH_MDIO | MIO77, FPGA Bank 502 | Pulled-up to +1.8V_PS. | | MDC | ETH_MDC | MIO76, FPGA Bank 502 |
| | MDIP[0] | PHY_MDI0_P | Pin2, J4 (RJ45) |
| | MDIN[0] | PHY_MDI0_N | Pin3, J4 (RJ45) |
| | MDIP[1] | PHY_MDI1_P | Pin4, J4 (RJ45) |
| | MDIN[1] | PHY_MDI1_N | Pin5, J4 (RJ45) |
| | MDIP[2] | PHY_MDI2_P | Pin6, J4 (RJ45) |
| | MDIN[2] | PHY_MDI2_N | Pin7, J4 (RJ45) |
| | MDIP[3] | PHY_MDI3_P | Pin8, J4 (RJ45) |
| | MDIN[3] | PHY_MDI3_N | Pin9, J4 (RJ45) |
| | LED[0] | PHY_LED0 | LED, J4 (RJ45) |
| | LED[1] | PHY_LED1 | LED, J4 (RJ45) |
| | CONFIG | - | - | Pulled-up to +1.8V_PS. | | XTAL_IN | ETH_XTAL_IN | Pin 3, U7 (Oscillator) |
| | RESETn | ETH_RST | MIO37, FPGA Bank 501 | Pulled-up to +1.8V_PS. | | RX_CLK | ETH_RXCK | MIO70, FPGA Bank 502 |
| | RX_CTRL | ETH_RXCTL | MIO75, FPGA Bank 502 |
| | RXD[0] | ETH_RXD0 | MIO71, FPGA Bank 502 |
| | RXD[1] | ETH_RXD1 | MIO72, FPGA Bank 502 |
| | RXD[2] | ETH_RXD2 | MIO73, FPGA Bank 502 |
| | RXD[3] | ETH_RXD3 | MIO74, FPGA Bank 502 |
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| Scroll Title |
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| anchor | Table_OBP_CLK_GEN |
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| title | Clock Generator Connections and Pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Clock Generator Pin | Signal Schematic Names | Connected to | Note |
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| REFP | - | Pin 3, U43 (Oscillator) |
| | REFSEL | REFSEL | - | Pulled-up to +3.3V. | | RESETN/SYNC | CLK_GEN_RESET | Pin B5, FPGA Bank 26 | Pulled-up to +3.3V. | | EEPROMSEL | EEPROMSEL | - | Pulled-up to +3.3V. | | SDA/GPIO2 | CLK_GEN_SDA | - (Default), MIO9, FPGA Bank 500 (R185/196 required), Pin 2, J14 (Pin Header required) | Pulled-up to +3.3V, . (Default) Pulled-up to +3.3V,. Pulled-up to +3.3V. | | SCL/GPIO3 | CLK_GEN_SCL | - (Default), MIO8, FPGA Bank 500 (R185/196 required), Pin 3, J14 (Pin Header required) | Pulled-up to +3.3V, . (Default) Pulled-up to +3.3V,. Pulled-up to +3.3V. | | OE/GPIO4 | - | - | Pulled-up to +3.3V. | Y1P | CLK_Y1_P / CLK_DP_P | Pin G19, FPGA Bank 505 | 27 MHz | | Y1N | CLK_Y1_N / CLK_DP_N | Pin G20, FPGA Bank 505 | 27 MHz | Y2P | CLK_Y2_P / CLK_USB_P | Pin J19, FPGA Bank 505 | 26 MHz | | Y2N | CLK_Y2_N / CLK_USB_N | Pin J20, FPGA Bank 505 | 26 MHz | Y3P | CLK_Y3_P / CLK_PCIe_P | Pin L19, FPGA Bank 505 | 100 MHz | | Y3N | CLK_Y3_N / CLK_PCIe_N | Pin L20, FPGA Bank 505 | 100 MHz | Y4P | CLK_Y4_P / SSD_RCLK_P | Pin 55, U5 (M.2) | 100 MHz | | Y4N | CLK_Y4_N / SSD_RCLK_N | Pin 53, U5 (M.2) | 100 MHz |
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| Scroll Title |
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| anchor | Table_PWR_PR |
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| title | Module power rails. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Power Rail Name | B2B ConnectorDirectionJM1 Pin | Notes | B2B Connector
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| VIN | JM2 Pin B2B Connector JM3 Pin | Direction | Notes | In | Supply Voltage |
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Bank Voltages
| Scroll Title |
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| anchor | Table_PWR_BV |
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| title | Zynq SoC bank voltages. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic Name | | Notes |
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| Bank 503 | +3.3V | 3.3 V |
| | Bank 26 | +3.3V | 3.3 V |
| | Bank 65 | +1.8V_PL | 1.8 V |
| | Bank 66 | +1.8V_PL | 1.8 V |
| | Bank 500 | +3.3V | 3.3 V |
| | Bank 501 | +3.3V | 3.3 V |
| | Bank 502 | +1.8V_PS | 1.8 V |
| | Bank 504 | +1.1V_LPDDR4 | 1.1 V |
| | Bank 505 | +0.85V_MGTRAVCC+1.8V_MGTRAVTT | 0.85 V1.8 V ??? |
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Technical Specifications
Absolute Maximum Ratings
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