Page History

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Page properties

hidden	true
id	Comments

Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
Scroll Title
anchor Table_tablename
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default style
widths sortByColumn 1
sortEnabled false
cellHighlighting true
Example Comment
1 2

The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

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Scroll Title

anchor	Figure_OV_BD
title	TE0802 Block Diagram

Scroll Ignore

draw.io Diagram

border	true
viewerToolbar	true

fitWindow	false
diagramName	TE08202-02_OV_BD
simpleViewer	false
width
diagramWidth	611
revision	1415

Scroll Only

Main Components

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Scroll Title

anchor	Figure_OV_MC
title	TE0802 Main Components (Picture shows Revision 01)

Scroll Ignore

draw.io Diagram

border	true
viewerToolbar	true
fitWindow	false
diagramName	TE0802_OV_MC
simpleViewer	false
width	diagramWidth	602
revision	8

Scroll Only

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Scroll Title

anchor	Table_OV_IDS
title	Initial Delivery State of Programmable Devices on the Module

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
SPI Flash (U16)	Not programmed
EEPROM (U2)	Not programmed	Except Ethernet MAC
EEPROM (U18)	Programmed	FTDI Configuration
LPDDR4 SDRAM (U13)	Not programmed

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Scroll Title

anchor	Table_OV_BP
title	Boot process.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

MODE Signal State	MODE0	MODE1	Boot Mode
MODE[1:0]	0	0	JTAG
MODE[1:0]	0	1	---
MODE[1:0]	1	0	QSPI(32)
MODE[1:0]	1	1	SD0(2.0)

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Scroll Title

anchor	Table_OV_RST
title	Reset process.

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widths

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Signal	Connected to	Note
POR_B	BTN6, Push Button	Connected to nRESET

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Scroll Title

anchor	Table_SIP_B2B
title	General I/O to Pin Header and Connectors Information

Scroll Table Layout

widths

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
sortByColumn	1
sortEnabled	false
cellHighlighting	true

FPGA Bank	Connector	I/O Signal Count	Voltage Level	Notes
Bank 503	J8, (Micro USB)	4 Single Ended	3.3 V	JTAG
Bank 500	J8, (Micro USB)	2 Single Ended	3.3 V	UART
Bank 500	J9, (Micro SD Card)	7 Single Ended	3.3 V
Bank 502	J4, (RJ45)	14 Single Ended	1.8 V
Bank 505	J11, (USB 3.0)	2 Differential Pairs	0.85 V
Bank 505	U5, (SSD M.2)	2 Differential Pairs	0.85 V
Bank 501	U5, (SSD M.2)	5 Single Ended	3.3 V
Bank 505	J3, (Display Port Connector)	2 Differential Pairs	0.85 V
Bank 26	J7, (D-Sub Host Socket)	2 Single Ended	3.3 V
Bank 65, 66,	J7, (D-Sub Host Socket)	12 Single Ended	1.8 V
Bank 65	J12, Headphone	3 Single Ended	1.8 V
Bank 500	J10, (Grove Connector)	2 Single Ended	3.3 V
Bank 26	J5 (Pmod Host Socket)	8 Single Ended	3.3 V
Bank 26	J6 (Pmod Host Socket)	8 Single Ended	3.3 V

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Scroll Title

anchor	Table_SIP_SD
title	Micro SD Card Connector Information

Scroll Table Layout

style

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic	Connected to	Notes
SD_DAT0	MIO 13, FPGA Bank 500
SD_DAT1	MIO 14, FPGA Bank 500
SD_DAT2	MIO 15, FPGA Bank 500
SD_DAT3	MIO 16, FPGA Bank 500
SD_CLK	MIO 22, FPGA Bank 500
SD_CMD	MIO 21, FPGA Bank 500
SD_CD	MIO 24, FPGA Bank 500

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Scroll Title

anchor	Table_SIP_RJ45
title	RJ45 Connector Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Pin	Schematic	ETH Pin
2	PHY_MDI0_P	MDIP[0]
3	PHY_MDI0_N	MDIN[0]
4	PHY_MDI1_P	MDIP[1]
5	PHY_MDI1_N	MDIN[1]
6	PHY_MDI2_P	MDIP[2]
7	PHY_MDI2_N	MDIN[2]
8	PHY_MDI3_P	MDIP[3]
9	PHY_MDI3_N	MDIN[3]

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Scroll Title

anchor	Table_SIP_USB
title	USB Socket Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Pin	Schematic	Corresponding Signals	Connected to
D-	USB0_D_N	USB0_DATA0...7	MIO 52...63 FPGA Bank 502
D+	USB0_D_P	USB0_DATA0...7	MIO 52...63 FPGA Bank 502
StdA_SSRX-	USB_RX2_N	-	FPGA Bank 505
StdA_SSRX+	USB_RX2_P	-	FPGA Bank 505
StdA_SSTX-	U3D2_N	USB_TX2_N	FPGA Bank 505
StdA_SSTX+	U3D2_P	USB_TX2_P	FPGA Bank 505

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Scroll Title

anchor	Table_SIP_SSD
title	SSD M.2 Connector Information

Scroll Table Layout

style

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Pin	Schematic	Connected to
PERn0/SATA-B+	SSD_RX3_N	Pin M22, FPGA Bank 505
PERp0/SATA-B-	SSD_RX3_P	Pin M21, FPGA Bank 505
PERn0/SATA-A+	SSD_TXC3_N	Pin K22, FPGA Bank 505
PERp0/SATA-A-	SSD_TXC3_P	Pin M21, FPGA Bank 505
REFCLKN	SSD_RCLK_N	Pin 9, Clock Generator U8
REFCLKP	SSD_RCLK_P	Pin 10, Clock Generator U8
DAS/DSS#	SSD_DAS	MIO35, FPGA Bank 501
DEVSLP	SSD_SLEEP	MIO32, FPGA Bank 501
PERST#	SSD_PERSTn	MIO31, FPGA Bank 501
CLKREQ#	SSD_CLKRQ	MIO33, FPGA Bank 501
PEWake#	SSD_WAKE	MIO34, FPGA Bank 501

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Scroll Title

anchor	Table_SIP_DP
title	Display Port Socket Information

Scroll Table Layout

widths

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic	Corresponding Signals	Connected to
DP_TX_L0_P/N	DP0_TX_P/N	Pin A19/A20, FPGA Bank 505
DP_TX_L1_P/N	DP1_TX_P/N	Pin C19/C20, FPGA Bank 505
DP_TX_AUX_P/N	DP_AUX_TX/RX	MIO27, MIO30, FPGA Bank 501

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Scroll Title

anchor	Table_SIP_VGA
title	D-Sub Connector Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic	Corresponding Signals	Connected to	Notes
VGA_RED	VGA_R0...3	Bank 65	Red Channel
VGA_GREEN	VGA_G0...3	Bank 65	Green Channel
VGA_BLUE	VGA_B0...3	Bank 66	Blue Channel
VGA_RGB_HSYNC	VGA_HS	Bank 26	Horizontal Sync
VGA_RGB_VSYNC	VGA_VS	Bank 26	Vertical Sync

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Scroll Title

anchor	Table_SIP_HP
title	Headphone Connector Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic	Connected to	Notes
JACKSNS	Pin F3, FPGA Bank 65
PWM_R	Pin F4, FPGA Bank 65
PWM_L	Pin E3, FPGA Bank 65

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Scroll Title

anchor	Table_SIP_Grove
title	Grove Connector Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic	Connected to	Notes
Grove_SCL0	MIO18, FPGA Bank 500
Grove_SDA0	MIO19, FPGA Bank 500

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Scroll Title

anchor	Table_SIP_PMOD
title	Pmod SMD Host Socket Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Designator	Signals	Connected to	Notes
J5	PMOD_A0...7	Bank 26
J6	PMOD_B0...7	Bank 26

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Scroll Title

anchor	Table_OBP
title	On board peripherals

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Chip/Interface	Designator	Notes
Quad SPI Flash Memory	U16
LPDDR4 SDRAM	U13
EEPROM	U2, U18
USB ULPI PHY	U22
Ethernet PHY	U6
FTDI FT2232H	U17
Clock Generator	U8
Oscillator	U7, U15, U19, U23, U43
7-Segment Display	D9
User LED	LED0...7
Push Button	BTN1...5
DIP Switch	S1, S7...8

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Scroll Title

anchor	Table_OBP_SPI
title	Quad SPI Interface MIOs and Pins

Scroll Table Layout

widths

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MIO Pin	Schematic	U16 Pin	Notes
MIO0	MIO0	B2	SPI_CLK
MIO1	MIO1	D2	SPI_DQ1
MIO2	MIO2	C4	SPI_DQ2
MIO3	MIO3	D4	SPI_DQ3
MIO4	MIO4	D3	SPI_DQ0
MIO5	MIO5	C2	SPI_CS

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Scroll Title

anchor	Table_OBP_FPGA_EEP
title	I2C FPGA EEPROM Interface MIOs and Pins

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

MIO Pin	Schematic	U2 Pin	Notes
MIO8	Int_SCL1	SCL
MIO9	Int_SDA1	SDA

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Scroll Title

anchor	Table_OBP_I2C_FPGA_EEP
title	I2C Address for FPGA EEPROM

Scroll Table Layout

widths

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MIO Pin	I2C Address	Designator	Notes
MIO8...9	0x50	U2

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Scroll Title

anchor	Table_OBP_FTDI_EEP
title	I2C FTDI EEPROM Interface MIOs and Pins

Scroll Table Layout

widths

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Pin	Schematic	U18 Pin	Notes
CS	EECS	1	FTDI
CLK	EECLK	2	FTDI
DIN/DO	EEDATA	3/4	FTDI

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Scroll Title

anchor	Table_OBP_USB
title	USB ULPI PHY Connections and Pins

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style

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

USB PHY Pin	Signal Schematic Names	Connected to
DATA0	USB0_DATA0	MIO56, FPGA Bank 502
DATA1	USB0_DATA1	MIO57, FPGA Bank 502
DATA2	USB0_DATA2	MIO54, FPGA Bank 502
DATA3	USB0_DATA3	MIO59, FPGA Bank 502
DATA4	USB0_DATA4	MIO60, FPGA Bank 502
DATA5	USB0_DATA5	MIO61, FPGA Bank 502
DATA6	USB0_DATA6	MIO62, FPGA Bank 502
DATA7	USB0_DATA7	MIO63, FPGA Bank 502
DIR	USB0_DIR	MIO53, FPGA Bank 502
NXT	USB0_NXP	MIO55, FPGA Bank 502
STP	USB0_STP	MIO58, FPGA Bank 502
RESETB	USB0_RST_N	MIO38, FPGA Bank 501
CPEN	USB0_VBUS_EN	Pin 1, U21 (Current-limited Power Switch)
VBUS	VBUS	Pin 8, U21 (Current-limited Power Switch). Pin 1, J11 (USB Connector)
ID	USB0_ID	Pulled-down to GND
DP	USB0_D_P	Pin 3, J11 (USB Connector)
DM	USB0_D_N	Pin 2, J11 (USB Connector)
REFCLK	USB0_RCLK	Pin 3, U23 (Oscillator)
CLKOUT	USB0_CLK	MIO52, FPGA Bank 502

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Scroll Title

anchor	Table_OBP_ETH
title	Ethernet PHY Connections and Pins

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Ethernet PHY Pin	Signal Schematic Names	ETH	Note
TXD0	ETH_TXD0	MIO65, FPGA Bank 502
TXD1	ETH_TXD1	MIO66, FPGA Bank 502
TXD2	ETH_TXD2	MIO67, FPGA Bank 502
TXD3	ETH_TXD3	MIO68, FPGA Bank 502
TX_CTRL	ETH_TXCTL	MIO69, FPGA Bank 502
TX_CLK	ETH_CLK	MIO64, FPGA Bank 502
MDIO	ETH_MDIO	MIO77, FPGA Bank 502	Pulled-up to +1.8V_PS.
MDC	ETH_MDC	MIO76, FPGA Bank 502
MDIP[0]	PHY_MDI0_P	Pin2, J4 (RJ45)
MDIN[0]	PHY_MDI0_N	Pin3, J4 (RJ45)
MDIP[1]	PHY_MDI1_P	Pin4, J4 (RJ45)
MDIN[1]	PHY_MDI1_N	Pin5, J4 (RJ45)
MDIP[2]	PHY_MDI2_P	Pin6, J4 (RJ45)
MDIN[2]	PHY_MDI2_N	Pin7, J4 (RJ45)
MDIP[3]	PHY_MDI3_P	Pin8, J4 (RJ45)
MDIN[3]	PHY_MDI3_N	Pin9, J4 (RJ45)
LED[0]	PHY_LED0	LED, J4 (RJ45)
LED[1]	PHY_LED1	LED, J4 (RJ45)
CONFIG	-	-	Pulled-up to +1.8V_PS.
XTAL_IN	ETH_XTAL_IN	Pin 3, U7 (Oscillator)
RESETn	ETH_RST	MIO37, FPGA Bank 501	Pulled-up to +1.8V_PS.
RX_CLK	ETH_RXCK	MIO70, FPGA Bank 502
RX_CTRL	ETH_RXCTL	MIO75, FPGA Bank 502
RXD[0]	ETH_RXD0	MIO71, FPGA Bank 502
RXD[1]	ETH_RXD1	MIO72, FPGA Bank 502
RXD[2]	ETH_RXD2	MIO73, FPGA Bank 502
RXD[3]	ETH_RXD3	MIO74, FPGA Bank 502

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Scroll Title

anchor	Table_OBP_FTDI
title	FTDI Chip Interfaces and Pins

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

FTDI Chip Pin	Signal Schematic Name	Connected to	Notes
ADBUS0	TCK	Pin H13, FPGA Bank 503	JTAG Interface
ADBUS1	TDI	Pin H12, FPGA Bank 503	JTAG Interface
ADBUS2	TDO	Pin J13, FPGA Bank 503	JTAG Interface
ADBUS3	TMS	Pin J12, FPGA Bank 503	JTAG Interface
BDBUS0	FT_B_TX	MIO10, FPGA Bank 500	UART
BDBUS1	FT_B_RX	MIO11, FPGA Bank 500	UART
EECS	EECS	Pin 1, U18 (EEPROM)
EECLK	EECLK	Pin 2, U18 (EEPROM)
EEDATA	EEDATA	Pin 3/4, U18 (EEPROM)
OSCI	-	Pin 3, U19 (Oscillator)
DM	D_N	Pin 2, J8 (Micro USB 2.0)
DP	D_P	Pin 3, J8 (Micro USB 2.0)

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Scroll Title

anchor	Table_OBP_CLK_GEN
title	Clock Generator Connections and Pins

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widths

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Clock Generator Pin	Signal Schematic Names	Connected to	Note
REFP	-	Pin 3, U43 (Oscillator)
REFSEL	REFSEL	-	Pulled-up to +3.3V.
RESETN/SYNC	CLK_GEN_RESET	Pin B5, FPGA Bank 26	Pulled-up to +3.3V.
EEPROMSEL	EEPROMSEL	-	Pulled-up to +3.3V.
SDA/GPIO2	CLK_GEN_SDA	- (Default) MIO9, FPGA Bank 500 (R185/196 required) Pin 2, J14 (Pin Header required)	Pulled-up to +3.3V. (Default) Pulled-up to +3.3V. Pulled-up to +3.3V.
SCL/GPIO3	CLK_GEN_SCL	- (Default) MIO8, FPGA Bank 500 (R185/196 required) Pin 3, J14 (Pin Header required)	Pulled-up to +3.3V. (Default) Pulled-up to +3.3V. Pulled-up to +3.3V.
OE/GPIO4	-	-	Pulled-up to +3.3V.
Y1P	CLK_Y1_P / CLK_DP_P	Pin G19, FPGA Bank 505	27 MHz
Y1N	CLK_Y1_N / CLK_DP_N	Pin G20, FPGA Bank 505	27 MHz
Y2P	CLK_Y2_P / CLK_USB_P	Pin J19, FPGA Bank 505	26 MHz
Y2N	CLK_Y2_N / CLK_USB_N	Pin J20, FPGA Bank 505	26 MHz
Y3P	CLK_Y3_P / CLK_PCIe_P	Pin L19, FPGA Bank 505	100 MHz
Y3N	CLK_Y3_N / CLK_PCIe_N	Pin L20, FPGA Bank 505	100 MHz
Y4P	CLK_Y4_P / SSD_RCLK_P	Pin 55, U5 (M.2)	100 MHz
Y4N	CLK_Y4_N / SSD_RCLK_N	Pin 53, U5 (M.2)	100 MHz

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Scroll Title

anchor	Table_OBP_CLK
title	Oscillators

Scroll Table Layout

widths

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Designator	Signal Schematic Names	Connected to	Description	Frequency
U7	ETH_XTAL_IN	Pin 34, U6 (Ethernet PHY)	Clock for Ethernet	25 MHz
U15	PS_CLK	Pin H14, FPGA Bank 503	Clock for FPGA	33 MHz
U23	USB_CLK / USB0_RCLK	Pin 26, U22 (USB PHY)	Clock for USB	52 MHz
U43	-	Pin 5, U8 (Clock Generator)	Clock for Clock Generator	25 MHz

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Scroll Title

anchor	Table_OBP_7SEG
title	7-Segment LED Pins

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Pin	Schematic	Connected to
A/L1	CA / SEG_CA	Pin E4, FPGA Bank 65
B/L2	CB / SEG_CB	Pin D3, FPGA Bank 65
C/L3	CC / SEG_CC	Pin N5, FPGA Bank 65
D	CD / SEG_CD	Pin P5, FPGA Bank 65
E	CE / SEG_CE	Pin N4, FPGA Bank 65
F	CF / SEG_CF	Pin C3, FPGA Bank 65
G	CG / SEG_CG	Pin R5, FPGA Bank 65
DP	CDP / SEG_CDP	Pin N3, FPGA Bank 65
A1	SEG_AN1	Pin A9, FPGA Bank 26
A2	SEG_AN2	Pin B9, FPGA Bank 26
A3	SEG_AN3	Pin A7, FPGA Bank 26
A4	SEG_AN4	Pin B6, FPGA Bank 26
L1-L3	SEG_AN	Pin A8, FPGA Bank 26

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Scroll Title

anchor	Table_OBP_LED
title	On-board LEDs

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic	Color	Connected to	Active Level	Note
LED0...7	Red	Bank 65	High
D12	Green	U9, PMIC	High

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Scroll Title

anchor	Table_OBP_PBTN
title	On-board Push Buttons

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
cellHighlighting	true

Designator	Schematic	Connected to	Functionality	Note
BTN_1	USER_BTN_UP	Pin U2, FPGA Bank 65	User Push Button	Pulled-up to +1.8V_PL.
BTN_2	USER_BTN_LEFT	Pin R1, FPGA Bank 65	User Push Button	Pulled-up to +1.8V_PL.
BTN_3	USER_BTN_OK	Pin T1, FPGA Bank 65	User Push Button	Pulled-up to +1.8V_PL.
BTN_4	USER_BTN_RIGHT	Pin U1, FPGA Bank 65	User Push Button	Pulled-up to +1.8V_PL.
BTN_5	USER_BTN_DOWN	Pin T2, FPGA Bank 65	User Push Button	Pulled-up to +1.8V_PL.
BTN_6	POR_B	Pin 38, U1 (PMIC), Pin 38, U9 (PMIC), Pin K12, FPGA Bank 503	Reset Button	Pulled-up to +3.3V.

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Scroll Title

anchor	Table_OBP_DIP_SWITCH
title	DIP Switches

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
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sortEnabled	false
cellHighlighting	true

Designator	Schematic	Connected to	Functionality	Note
S1A	MODE0	Pin J16, FPGA Bank 503	DIP	Pulled-down to GND.
S1B	MODE1	Pin H15, FPGA Bank 503	DIP	Pulled-down to GND.
S1C	USER_CFG0	Pin A4, FPGA Bank 66	DIP	Pulled-down to GND.
S1D	USER_CFG1	Pin B4, FPGA Bank 66	DIP	Pulled-down to GND.
S7A	USER_SW7	Pin M5, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S7B	USER_SW6	Pin M4, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S7C	USER_SW5	Pin J2, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S7D	USER_SW4	Pin K1, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S8A	USER_SW3	Pin L1, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S8B	USER_SW2	Pin M1, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S8C	USER_SW1	Pin P2, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.
S8D	USER_SW0	Pin P3, FPGA Bank 65	DIP	Pulled-up to +1.8V_PL.

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Scroll Title

anchor	Table_PWR_PC
title	Power Consumption

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default	style
sortByColumn	1
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cellHighlighting	true

Power Input Pin	Typical Current
VIN	TBD*

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Scroll Title

anchor	Figure_PWR_PD
title	Power Distribution

Scroll Ignore

draw.io Diagram

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viewerToolbar	true
fitWindow	false
diagramName	TE0802_PWR_PD
simpleViewer	false
width	diagramWidth	561
revision	2

Scroll Only

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Scroll Title

anchor	Table_PWR_PR
title	Module power rails.

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cellHighlighting	true

Power Rail Name	Direction	Notes
VIN	In	Supply Voltage

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Scroll Title

anchor	Table_PWR_BV
title	Zynq SoC bank voltages.

Scroll Table Layout

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sortDirection	ASC
repeatTableHeaders	default	style
widths	sortByColumn	1
sortEnabled	false
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Bank	Schematic Name	Voltage
Bank 26	+3.3V	3.3 V
Bank 65	+1.8V_PL	1.8 V
Bank 66	+1.8V_PL	1.8 V
Bank 500	+3.3V	3.3 V
Bank 501	+3.3V	3.3 V
Bank 502	+1.8V_PS	1.8 V
Bank 503	+3.3V	3.3 V
Bank 504	+1.1V_LPDDR4	1.1 V
Bank 505	+0.85V_MGTRAVCC	0.85 V

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Scroll Title

anchor	Table_TS_AMR
title	PS absolute maximum ratings

Scroll Table Layout

style

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
widths	sortByColumn	1
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cellHighlighting	true

Symbols	Description	Min	Max	Unit
VIN	Input Supply Voltage (J13)	4	5.5	V

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Scroll Title

anchor	Table_TS_ROC
title	Recommended operating conditions.

Scroll Table Layout

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Parameter	Min	Max	Units	Reference Document
VIN	4	5.5	V

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Scroll Title

anchor	Table_VCP_SO
title	Trenz Electronic Shop Overview

Scroll Table Layout

widths

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Trenz shop TE0728 overview page
English page	German page

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Scroll Title

anchor	Table_RH_HRH
title	Hardware Revision History

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Date	Revision	Changes
-
	02	Added suppressor 1SMA5.0AT3G on power input; Changed OV and UV protection range; Changed VGA schematic: USB page: VBUS resistor changed on 1K; The revision has been renamed as TE0802-02-2AEV2-A
	01

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Scroll Title

anchor	Table_RH_DCH
title	Document change history.

Scroll Table Layout

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Date

Revision

Contributor

Description

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

Page info

infoType	Current version
prefix	v.
type	Flat
showVersions	false

Page info

infoType	Modified by
type	Flat
showVersions	false

Initial Release

--

all

Page info

infoType	Modified users
type	Flat
showVersions	false

--

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Trenz Electronic Documentation

Versions Compared

Old Version 16

New Version 17

Key

Main Components