Page History

...

...

...

...

Micro USB 2.0

...

FTDI FT2232 (U17) can be accessed through micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.

Micro SD Card

...

TEI0802 is equipped with a micro SD card connector (J9).

Scroll Title
anchor Table_SIP_SD title Micro SD Card Connector Information
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Schematic Connected to Notes SD_DAT0 MIO 13, FPGA Bank 500 SD_DAT1 MIO 14, FPGA Bank 500 SD_DAT2 MIO 15, FPGA Bank 500 SD_DAT3 MIO 16, FPGA Bank 500 SD_CLK MIO 22, FPGA Bank 500 SD_CMD MIO 21, FPGA Bank 500 SD_CD MIO 24, FPGA Bank 500

RJ45

...

TEI0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connectors J4 is connected to Ethernet PHYs U6.

Scroll Title
anchor Table_SIP_RJ45 title RJ45 Connector Information
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Pin Schematic ETH Pin Notes 2 PHY_MDI0_P MDIP[0] 3 PHY_MDI0_N MDIN[0] 4 PHY_MDI1_P MDIP[1] 5 PHY_MDI1_N MDIN[1] 6 PHY_MDI2_P MDIP[2] 7 PHY_MDI2_N MDIN[2] 8 PHY_MDI3_P MDIP[3] 9 PHY_MDI3_N MDIN[3]

USB

...

TEI0802 is equipped with a USB connector (J11).

Scroll Title
anchor Table_SIP_USB title USB Socket Information
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Pin Schematic Corresponding Signals Connected to Notes D- USB0_D_N USB0_DATA0...7 MIO 52...63 FPGA Bank 502 D+ USB0_D_P USB0_DATA0...7 MIO 52...63 FPGA Bank 502 StdA_SSRX- USB_RX2_N - FPGA Bank 505 StdA_SSRX+ USB_RX2_P - FPGA Bank 505 StdA_SSTX- U3D2_N USB_TX2_N FPGA Bank 505 StdA_SSTX+ U3D2_P USB_TX2_P FPGA Bank 505

SSD M.2

...

TEI0802 is equipped with a SSD M.2 connector (U5).

Scroll Title
anchor Table_SIP_SSD title SSD M.2 Connector Information
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Pin Schematic Connected to Notes PERn0/SATA-B+ SSD_RX3_N Pin M22, FPGA Bank 505 PERp0/SATA-B- SSD_RX3_P Pin M21, FPGA Bank 505 PERn0/SATA-A+ SSD_TXC3_N Pin K22, FPGA Bank 505 PERp0/SATA-A- SSD_TXC3_P Pin M21, FPGA Bank 505 REFCLKN SSD_RCLK_N Pin 9, Clock Generator U8 REFCLKP SSD_RCLK_P Pin 10, Clock Generator U8 DAS/DSS# SSD_DAS MIO35, FPGA Bank 501 DEVSLP SSD_SLEEP MIO32, FPGA Bank 501 PERST# SSD_PERSTn MIO31, FPGA Bank 501 CLKREQ# SSD_CLKRQ MIO33, FPGA Bank 501 PEWake# SSD_WAKE MIO34, FPGA Bank 501

Display Port

...

TEI0802 is equipped with a Display Port connector (J3).

Scroll Title
anchor Table_SIP_DP title Display Port Socket Information
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Schematic Corresponding Signals Connected to Notes DP_TX_L0_P/N DP0_TX_P/N Pin A19/A20, FPGA Bank 505 DP_TX_L1_P/N DP1_TX_P/N Pin C19/C20, FPGA Bank 505 DP_TX_AUX_P/N DP_AUX_TX/RX MIO27, MIO30, FPGA Bank 501

D-Sub

...

TEI0802 is equipped with a D-Sub connector (J7).

Scroll Title
anchor Table_SIP_VGA title D-Sub Connector Information
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Schematic Corresponding Signals Connected to Notes VGA_RED VGA_R0...3 Bank 65 Red Channel VGA_GREEN VGA_G0...3 Bank 65 Green Channel VGA_BLUE VGA_B0...3 Bank 66 Blue Channel VGA_RGB_HSYNC VGA_HS Bank 26 Horizontal Sync VGA_RGB_VSYNC VGA_VS Bank 26 Vertical Sync

Headphone

...

TEI0802 is equipped with a headphone connector (J12).

Scroll Title
anchor Table_SIP_HP title Headphone Connector Information
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Schematic Connected to Notes JACKSNS Pin F3, FPGA Bank 65 PWM_R Pin F4, FPGA Bank 65 PWM_L Pin E3, FPGA Bank 65

Grove

...

TEI0802 is equipped with a grove connector (J10).

Scroll Title
anchor Table_SIP_Grove title Grove Connector Information
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Schematic Connected to Notes Grove_SCL0 MIO18, FPGA Bank 500 Grove_SDA0 MIO19, FPGA Bank 500

Pmod

...

TEI0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.

...

Scroll Title
anchor Table_OBP title On-board peripheralsPeripherals
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Chip/Interface Designator Notes Quad SPI Flash Memory U16 LPDDR4 SDRAM U13 EEPROM U2, U18 USB ULPI PHY U22 Ethernet PHY U6 FTDI FT2232H U17 Clock Generator U8 Oscillator U7, U15, U19, U23, U43 7-Segment Display D9 User LED LED0...7 Push Button BTN1...5 DIP Switch S1, S7...8

...

Scroll Title
anchor Table_OBP_FTDI_EEP title I2C FTDI EEPROM Interface MIOs and Pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Pin Schematic U18 Pin Notes CS EECS 1 FTDI CLK EECLK 2 FTDI DIN/DO EEDATA 3/4 FTDI

...

Scroll Title
anchor Table_PWR_PR title Module power rails.Power Rails
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Power Rail Name Direction Notes VIN In Supply Voltage +5V Out J1...2 +3.3V Out J14, J10

...

Scroll Title
anchor Table_PWR_BV title Zynq SoC bank voltages.Bank Voltages
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Bank           Schematic Name Voltage Notes Bank 26 +3.3V 3.3 V Bank 65 +1.8V_PL 1.8 V Bank 66 +1.8V_PL 1.8 V Bank 500 +3.3V 3.3 V Bank 501 +3.3V 3.3 V Bank 502 +1.8V_PS 1.8 V Bank 503 +3.3V 3.3 V Bank 504 +1.1V_LPDDR4 1.1 V Bank 505 +0.85V_MGTRAVCC 0.85 V

...

Scroll Title
anchor Table_TS_AMR title PS absolute maximum ratingsAbsolute Maximum Ratings
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Symbols Description Min Max Unit VIN Input Supply Voltage (J13) -40 50 V

...

Scroll Title
anchor Table_TS_ROC title Recommended operating conditions.Operating Conditions
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Parameter Min Max Units Reference Document VIN 4 5.5 V

...

Scroll Title
anchor Figure_RV_HRN title Board hardware revision number.Hardware Revision Number
Scroll Ignore draw.io Diagram border true viewerToolbar true fitWindow false diagramDisplayName lbox true revision 2 diagramName TE0802_RV_HRN simpleViewer true width links auto tbstyle top diagramWidth 271 Scroll Only

...

Scroll Title
anchor Table_RH_DCH title Document change history.Change History
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true Date Revision Contributor Description Page info infoType Modified date dateFormat yyyy-MM-dd type Flat Page info infoType Current version prefix v. type Flat showVersions false Page info infoType Modified by type Flat showVersions false Initial Release -- all Page info infoType Modified users type Flat showVersions false --

...