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The Trenz Electronic TE0802 is an evalution module. Other assymbly assembly options for the FPGA and the memory chips are available. Please ask contact us for further information.

Refer to http://trenz.org/te0802-info for the current online version of this manual and other available documentation.

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MPSoC: Xilinx Zynq XCZU2CG-1SBVA484E
SDRAM: LPDDR4-3733 8Gb 256Mx32
Storages:
- SPI Flash 256Mb (32M x 8) 133 MHz
- microSD Card
- M.2 SSD PCIe
Display Interfaces:
- DisplayPort
- VGA
- 4 Digit 7-Segment LED Display
- 8 LEDs
Audio:
- 3.5 mm Jack (PWM Output)
Input:
- 5 User Buttons
- 8 Bit Slide Switches
- Reset Button
User I/O:
- 2x Pmod Connector
Communication:
- 1GB Ethernet RJ45
- USB 3.0 Host (Type A Connector)
Debug
- USB JTAG/UART microUSB
Power
- 5 V +/- 10%
- ~3.5 W
Dimension: 100mm x 100mm

Block Diagram

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id	Comments

add drawIO object here.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

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Scroll Title

anchor	Figure_OV_BD
title	TE0802 Block Diagram

Scroll Ignore

draw.io Diagram

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viewerToolbar	true

fitWindow	false
diagramDisplayName
lbox	true
revision	46
diagramName	TEMP
simpleViewer	false
width
links	auto
tbstyle	hidden
diagramWidth	638

Scroll Only

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Scroll Title

anchor	Table_OV_BP
title	Boot Process

Scroll Table Layout

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sortDirection	ASC
repeatTableHeaders	default
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cellHighlighting	true

MODE Signal State	MODE0 S1-1	MODE1 S1-2	Boot Mode
MODE[1:0]=00b	OFF	OFF	JTAG
MODE[1:0]=01b	OFF	ON	-
MODE[1:0]=10b	ON	OFF	QSPI(32)
MODE[1:0]=11b	ON	ON	SD0(2.0)

Scroll Title

anchor	Table_OV_RST
title	Reset Process

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Signal	Connected to	Note
POR_B	BTN6, Push Button	Connected to nRESET

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Trenz Electronic Documentation

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Block Diagram