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TEI0802 is equipped with a Micro USB2.0 B connector J8 and a USB3.0 connector J11.
FTDI FT2232 (U17) can be accessed through Micro USB 2.0 B connector (J8) for JTAG (channel A). Channel B is connected to the FPGA and can be used for UART.
| Scroll Title |
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| anchor | Table_SIP_USBUSB2 |
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| title | USB USB2.0 B Socket Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Corresponding Signals | USB0_D_N | USB0_DATA0...7 | MIO 52...63 FPGA Bank 502 | D+ | USB0_D_P | USB0_DATA0...7 | MIO 52...63 FPGA Bank 502 | StdA_SSRX- | USB_RX2_N | - | FPGA Bank 505 | | D_N | FTDI, U17 |
| | D+ | D_P | FTDI, U17 |
| | Vbus | USB_VBUS | GND |
StdA_SSRX+ | USB_RX2_P | - | FPGA Bank 505 | StdA_SSTX- | U3D2_N | USB_TX2_N | FPGA Bank 505 | StdA_SSTX+ | U3D2_P | USB_TX2_P | FPGA Bank 505
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| Scroll Title |
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| anchor | Table_SIP_USBUSB3 |
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| title | USB USB3.0 A Socket Information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Corresponding Signals | Connected to | Notes |
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| D- | USB0_D_N | USB PHY, U22 |
| | D+ | USB0_D_P | USB PHY, U22 |
| | StdA_SSRX- | USB_RX2_N |
- | FPGA Bank 505 |
| | StdA_SSRX+ | USB_RX2_P |
-U3D2_N | | USB_TX2_N | FPGA Bank 505 |
| | StdA_SSTX+ |
U3D2_P | USB_TX2_P | FPGA Bank 505 |
| | VBUS | VBUS | USB PHY, U22 |
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SSD M.2
TEI0802 is equipped with a SSD M.2 connector (U5).
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On-board Peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Quad SPI Flash Memory
| Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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| Scroll Title |
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| anchor | Table_OBP_CLK_GEN |
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| title | Clock Generator Connections and Pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Clock Generator Pin | Signal Schematic Names | Connected to | Note |
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| REFP | - | Pin 3, U43 (Oscillator) |
| | REFSEL | REFSEL | - | Pulled-up to +3.3V. | | RESETN/SYNC | CLK_GEN_RESET | Pin B5, FPGA Bank 26 | Pulled-up to +3.3V. | | EEPROMSEL | EEPROMSEL | - | Pulled-up to +3.3V. | | SDA/GPIO2 | CLK_GEN_SDA | - (Default) MIO9, FPGA Bank 500 (R185/196 required) Pin 2, J14 (Pin Header required) | Pulled-up to +3.3V. (Default) Pulled-up to +3.3V. Pulled-up to +3.3V. | | SCL/GPIO3 | CLK_GEN_SCL | - (Default) MIO8, FPGA Bank 500 (R185/196 required) Pin 3, J14 (Pin Header required) | Pulled-up to +3.3V. (Default) Pulled-up to +3.3V. Pulled-up to +3.3V. | | OE/GPIO4 | - | - | Pulled-up to +3.3V. | Y1P | CLK_Y1_P / CLK_DP_P | Pin G19, FPGA Bank 505 | 27 MHz | | Y1N | CLK_Y1_N / CLK_DP_N | Pin G20, FPGA Bank 505 | 27 MHz | Y2P | CLK_Y2_P / CLK_USB_P | Pin J19, FPGA Bank 505 | 26 MHz | | Y2N | CLK_Y2_N / CLK_USB_N | Pin J20, FPGA Bank 505 | 26 MHz | Y3P | CLK_Y3_P / CLK_PCIe_P | Pin L19, FPGA Bank 505 | 100 MHz | | Y3N | CLK_Y3_N / CLK_PCIe_N | Pin L20, FPGA Bank 505 | 100 MHz | Y4P | CLK_Y4_P / SSD_RCLK_P | Pin 55, U5 (M.2) | 100 MHz | | Y4N | CLK_Y4_N / SSD_RCLK_N | Pin 53, U5 (M.2) | 100 MHz |
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Clock Sources
| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Oscillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Signal Schematic Names | Connected to | Description | Frequency | Note |
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| U7 | ETH_XTAL_IN | Pin 34, U6 (Ethernet PHY) | Clock for Ethernet | 25 MHz |
| | U15 | PS_CLK | Pin H14, FPGA Bank 503 | Clock for FPGA | 33 MHz |
| | U23 | USB_CLK / USB0_RCLK | Pin 26, U22 (USB PHY) | Clock for USB | 52 MHz |
| | U43 | - | Pin 5, U8 (Clock Generator) | Clock for Clock Generator | 25 MHz |
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| Scroll Title |
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| anchor | Figure_PWR_PD |
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| title | Power Distribution |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 2 |
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| diagramName | TE0802_PWR_PD |
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| simpleViewer | true |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 561 |
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| Scroll Only |
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 Image Modified
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Power-On Sequence
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Module size: 100 mm × 100 mm. Please download the assembly diagram for exact numbers.
PCB thickness: 1,.48 mm
| Page properties |
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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM. For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below: https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF
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