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Overview

The Trenz Electronic TEI0802 TE0802 is an evaluation module integrating a . Other assembly options for the FPGA and the memory chips are available. Please contact us for further information.

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Scroll Title

anchor	Table_SIP_B2B
title	General I/O to Pin Header and Connectors Information

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orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

FPGA Bank	Connector	I/O Signal Count	Voltage Level	Notes
Bank 503	Micro USB, J8	4 Single Ended	3.3 V	JTAG
Bank 500	Micro USB, J8	2 Single Ended	3.3 V	UART
Bank 500	Micro SD Card, J9	7 Single Ended	3.3 V
Bank 502	Micro SD Card, J4	14 Single Ended	1.8 V
Bank 505	USB 3.0, J11	2 Differential Pairs	0.85 V
Bank 505	SSD M.2, U5	2 Differential Pairs	0.85 V
Bank 501	SSD M.2, U5	5 Single Ended	3.3 V
Bank 505	Display Port Connector, J3	2 Differential Pairs	0.85 V
Bank 26	D-Sub Host Socket, J7	2 Single Ended	3.3 V
Bank 65, 66,	D-Sub Host Socket, J7	12 Single Ended	1.8 V
Bank 65	Earphone, J12	3 Single Ended	1.8 V
Bank 500	Grove Connector, J10	2 Single Ended	3.3 V
Bank 26	Pmod Host Socket, J5	8 Single Ended	3.3 V
Bank 26	Pmod Host Socket, J6	8 Single Ended	3.3 V

Micro SD Card

TEI0802 TE0802 is equipped with a micro SD card connector (J9).

Scroll Title

anchor	Table_SIP_SD
title	Micro SD Card Connector Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic	Connected to	Notes
SD_DAT0	MIO 13, FPGA Bank 500
SD_DAT1	MIO 14, FPGA Bank 500
SD_DAT2	MIO 15, FPGA Bank 500
SD_DAT3	MIO 16, FPGA Bank 500
SD_CLK	MIO 22, FPGA Bank 500
SD_CMD	MIO 21, FPGA Bank 500
SD_CD	MIO 24, FPGA Bank 500

RJ45

TEI0802 TE0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connector J4 is connected to Ethernet PHYs U6.

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anchor	Table_SIP_RJ45
title	RJ45 Connector Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Pin	Schematic	ETH Pin
2	PHY_MDI0_P	MDIP[0]
3	PHY_MDI0_N	MDIN[0]
4	PHY_MDI1_P	MDIP[1]
5	PHY_MDI1_N	MDIN[1]
6	PHY_MDI2_P	MDIP[2]
7	PHY_MDI2_N	MDIN[2]
8	PHY_MDI3_P	MDIP[3]
9	PHY_MDI3_N	MDIN[3]

USBs

TEI0802 TE0802 is equipped with a Micro USB2.0 B connector J8 and a USB3.0 connector J11.

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Scroll Title

anchor	Table_SIP_USB3
title	USB3.0 A Socket Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

USB3.0 Pin	Schematic	Connected to
D-	USB0_D_N	USB PHY, U22
D+	USB0_D_P	USB PHY, U22
StdA_SSRX-	USB_RX2_N	FPGA Bank 505
StdA_SSRX+	USB_RX2_P	FPGA Bank 505
StdA_SSTX-	USB_TX2_N	FPGA Bank 505
StdA_SSTX+	USB_TX2_P	FPGA Bank 505
VBUS	VBUS	USB PHY, U22

SSD M.2

TEI0802 TE0802 is equipped with a SSD M.2 connector (U5).

Scroll Title

anchor	Table_SIP_SSD
title	SSD M.2 Connector Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Pin	Schematic	Connected to
PERn0/SATA-B+	SSD_RX3_N	Pin M22, FPGA Bank 505
PERp0/SATA-B-	SSD_RX3_P	Pin M21, FPGA Bank 505
PERn0/SATA-A+	SSD_TXC3_N	Pin K22, FPGA Bank 505
PERp0/SATA-A-	SSD_TXC3_P	Pin M21, FPGA Bank 505
REFCLKN	SSD_RCLK_N	Pin 9, Clock Generator U8
REFCLKP	SSD_RCLK_P	Pin 10, Clock Generator U8
DAS/DSS#	SSD_DAS	MIO35, FPGA Bank 501
DEVSLP	SSD_SLEEP	MIO32, FPGA Bank 501
PERST#	SSD_PERSTn	MIO31, FPGA Bank 501
CLKREQ#	SSD_CLKRQ	MIO33, FPGA Bank 501
PEWake#	SSD_WAKE	MIO34, FPGA Bank 501

Display Port

TEI0802 TE0802 is equipped with a Display Port connector (J3).

Scroll Title

anchor	Table_SIP_DP
title	Display Port Socket Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic	Corresponding Signals	Connected to
DP_TX_L0_P/N	DP0_TX_P/N	Pin A19/A20, FPGA Bank 505
DP_TX_L1_P/N	DP1_TX_P/N	Pin C19/C20, FPGA Bank 505
DP_TX_AUX_P/N	DP_AUX_TX/RX	MIO27, MIO30, FPGA Bank 501

D-Sub

TEI0802 TE0802 is equipped with a D-Sub connector (J7).

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Scroll Title

anchor	Table_SIP_HP
title	Headphone Connector Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic	Connected to	Notes
JACKSNS	Pin F3, FPGA Bank 65
PWM_R	Pin F4, FPGA Bank 65
PWM_L	Pin E3, FPGA Bank 65

Grove

TEI0802 TE0802 is equipped with a grove connector (J10).

Scroll Title

anchor	Table_SIP_Grove
title	Grove Connector Information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Schematic	Connected to	Notes
Grove_SCL0	MIO18, FPGA Bank 500
Grove_SDA0	MIO19, FPGA Bank 500

Pmod

TEI0802 TE0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.

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Scroll Title

anchor	Table_OBP_USB
title	USB ULPI PHY Connections and Pins

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

USB PHY Pin	Signal Schematic Names	Connected to
DATA0	USB0_DATA0	MIO56, FPGA Bank 502
DATA1	USB0_DATA1	MIO57, FPGA Bank 502
DATA2	USB0_DATA2	MIO54, FPGA Bank 502
DATA3	USB0_DATA3	MIO59, FPGA Bank 502
DATA4	USB0_DATA4	MIO60, FPGA Bank 502
DATA5	USB0_DATA5	MIO61, FPGA Bank 502
DATA6	USB0_DATA6	MIO62, FPGA Bank 502
DATA7	USB0_DATA7	MIO63, FPGA Bank 502
DIR	USB0_DIR	MIO53, FPGA Bank 502
NXT	USB0_NXP	MIO55, FPGA Bank 502
STP	USB0_STP	MIO58, FPGA Bank 502
RESETB	USB0_RST_N	MIO38, FPGA Bank 501
CPEN	USB0_VBUS_EN	Pin 1, U21 (Current-limited Power Switch)
VBUS	VBUS	Pin 8, U21 (Current-limited Power Switch). Pin 1, J11 (USB Connector)
ID	USB0_ID	Pulled-down to GND
DP	USB0_D_P	Pin 3, J11 (USB Connector)
DM	USB0_D_N	Pin 2, J11 (USB Connector)
REFCLK	USB0_RCLK	Pin 3, U23 (Oscillator)
CLKOUT	USB0_CLK	MIO52, FPGA Bank 502

Ethernet PHY

The TEI0802 TE0802 is equipped with an Ethernet PHY (U6) which is connected to RJ45 (J) connector.

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Scroll Title

anchor	Table_OBP_FTDI
title	FTDI Chip Interfaces and Pins

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

FTDI Chip Pin	Signal Schematic Name	Connected to	Notes
ADBUS0	TCK	Pin H13, FPGA Bank 503	JTAG Interface
ADBUS1	TDI	Pin H12, FPGA Bank 503	JTAG Interface
ADBUS2	TDO	Pin J13, FPGA Bank 503	JTAG Interface
ADBUS3	TMS	Pin J12, FPGA Bank 503	JTAG Interface
BDBUS0	FT_B_TX	MIO10, FPGA Bank 500	UART
BDBUS1	FT_B_RX	MIO11, FPGA Bank 500	UART
EECS	EECS	Pin 1, U18 (EEPROM)
EECLK	EECLK	Pin 2, U18 (EEPROM)
EEDATA	EEDATA	Pin 3/4, U18 (EEPROM)
OSCI	-	Pin 3, U19 (Oscillator)
DM	D_N	Pin 2, J8 (Micro USB 2.0)
DP	D_P	Pin 3, J8 (Micro USB 2.0)

Clock Generator

The TEI0802 TE0802 is equipped with a clock generator (U8).

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Scroll Title

anchor	Table_OBP_CLK
title	Oscillators

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Designator	Signal Schematic Names	Connected to	Description	Frequency
U7	ETH_XTAL_IN	Pin 34, U6 (Ethernet PHY)	Clock for Ethernet	25 MHz
U15	PS_CLK	Pin H14, FPGA Bank 503	Clock for FPGA	33 MHz
U23	USB_CLK / USB0_RCLK	Pin 26, U22 (USB PHY)	Clock for USB	52 MHz
U43	-	Pin 5, U8 (Clock Generator)	Clock for Clock Generator	25 MHz

7-Segment Display

The TEI0802 TE0802 has a 4-Digit-7-Segment LED display.

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Trenz Electronic Documentation

Versions Compared

Old Version 42

New Version 43

Key

Overview

Micro SD Card

RJ45

USBs

SSD M.2

Display Port

D-Sub

Grove

Pmod

Ethernet PHY

Clock Generator

7-Segment Display