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| Scroll Title |
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| anchor | Table_SIP_VGA |
|---|
| title | D-Sub Connector Information |
|---|
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| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | Corresponding Signals | Connected to | Notes |
|---|
| VGA_RED | VGA_R0...3 | Bank 65 | Red Channel | | VGA_GREEN | VGA_G0...3 | Bank 65 | Green Channel | | VGA_BLUE | VGA_B0...3 | Bank 66 | Blue Channel | | VGA_RGB_HSYNC | VGA_HS | Bank 26 | Horizontal Sync | | VGA_RGB_VSYNC | VGA_VS | Bank 26 | Vertical Sync |
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HeadphoneHeadphone
TE0802 is equipped with a headphone connector (J12).
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The TE0802 evaluation board has 1 GByte volatile LPDDR4 SDRAM IC (U13) for storing user application code and data. The details depends on the assembly option.
- Part number: K4F8E304HB_MGCJ0000_200FMGC
- Supply voltage: 1.8 V
- Speed: ????
- NOR Flash
- 3733 Mbps
- Temperature: -55 to +125 C
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| Scroll Title |
|---|
| anchor | Table_OBP_LED |
|---|
| title | On-board LEDs |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
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| Schematic | Color | Connected to | Active Level | Note |
|---|
| LED0...7 | Red | Bank 65 | High |
| | D12 | Green | U9, PMIC | High | POWER_OK |
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Push Button
| Scroll Title |
|---|
| anchor | Table_OBP_PBTN |
|---|
| title | On-board Push Buttons |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
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| Designator | Schematic | Connected to | Functionality | Note |
|---|
| BTN_1 | USER_BTN_UP | Pin U2, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | | BTN_2 | USER_BTN_LEFT | Pin R1, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | | BTN_3 | USER_BTN_OK | Pin T1, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | | BTN_4 | USER_BTN_RIGHT | Pin U1, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | | BTN_5 | USER_BTN_DOWN | Pin T2, FPGA Bank 65 | User Push Button | Pulled-up to +1.8V_PL. | | BTN_6 | POR_B | Pin 38, U1 (PMIC), Pin 38, U9 (PMIC), Pin K12, FPGA Bank 503 | Reset Button | Pulled-up to +3.3V. |
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