Page History

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Scroll Title

anchor	Table_SIP_PMOD
title	Pmod SMD Host Socket Information

Scroll Table Layout

Designator	Signals	Connected to	Notes
J5	PMOD_A0...7	Bank 26
J6	PMOD_B0...7	Bank 26

Scroll Title

anchor	Table_SIP_TestPoint
title	Test Points Information

Scroll Table Layout

Test Point	Signals	B2B Connector	Notes
1		JB3-124
2		JB1-22
3		JB1-34
4		JB1-36
5		JB1-24
6		JB3-81
7		JB3-88
8		JB3-87
9		JB3-82
10		JB3-141
11		JB3-148
12		JB3-147
13		JB3-142
14		JB1-165...168
15		-
16		JB1-147...148
17-18		-

On-board Peripherals

Page properties

hidden	true
id	Comments

Notes :

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The TE0802 is equipped with an Ethernet PHY (U6) which is connected to RJ45 (JJ4) connector.

Scroll Title

anchor	Table_OBP_ETH
title	Ethernet PHY Connections and Pins

Scroll Table Layout

Ethernet PHY Pin	Signal Schematic Names	ETH	Note
TXD0	ETH_TXD0	MIO65, FPGA Bank 502
TXD1	ETH_TXD1	MIO66, FPGA Bank 502
TXD2	ETH_TXD2	MIO67, FPGA Bank 502
TXD3	ETH_TXD3	MIO68, FPGA Bank 502
TX_CTRL	ETH_TXCTL	MIO69, FPGA Bank 502
TX_CLK	ETH_CLK	MIO64, FPGA Bank 502
MDIO	ETH_MDIO	MIO77, FPGA Bank 502	Pulled-up to +1.8V_PS.
MDC	ETH_MDC	MIO76, FPGA Bank 502
MDIP[0]	PHY_MDI0_P	Pin2, J4 (RJ45)
MDIN[0]	PHY_MDI0_N	Pin3, J4 (RJ45)
MDIP[1]	PHY_MDI1_P	Pin4, J4 (RJ45)
MDIN[1]	PHY_MDI1_N	Pin5, J4 (RJ45)
MDIP[2]	PHY_MDI2_P	Pin6, J4 (RJ45)
MDIN[2]	PHY_MDI2_N	Pin7, J4 (RJ45)
MDIP[3]	PHY_MDI3_P	Pin8, J4 (RJ45)
MDIN[3]	PHY_MDI3_N	Pin9, J4 (RJ45)
LED[0]	PHY_LED0	LED, J4 (RJ45)
LED[1]	PHY_LED1	LED, J4 (RJ45)
CONFIG	-	-	Pulled-up to +1.8V_PS.
XTAL_IN	ETH_XTAL_IN	Pin 3, U7 (Oscillator)
RESETn	ETH_RST	MIO37, FPGA Bank 501	Pulled-up to +1.8V_PS.
RX_CLK	ETH_RXCK	MIO70, FPGA Bank 502
RX_CTRL	ETH_RXCTL	MIO75, FPGA Bank 502
RXD[0]	ETH_RXD0	MIO71, FPGA Bank 502
RXD[1]	ETH_RXD1	MIO72, FPGA Bank 502
RXD[2]	ETH_RXD2	MIO73, FPGA Bank 502
RXD[3]	ETH_RXD3	MIO74, FPGA Bank 502

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