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| Scroll Title |
|---|
| anchor | Table_SIP_SD |
|---|
| title | Micro SD Card Connector Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic | Connected to | Notes |
|---|
| SD_DAT0 | MIO 13, FPGA Bank 500 |
| | SD_DAT1 | MIO 14, FPGA Bank 500 |
| | SD_DAT2 | MIO 15, FPGA Bank 500 |
| | SD_DAT3 | MIO 16, FPGA Bank 500 |
| | SD_CLK | MIO 22, FPGA Bank 500 |
| | SD_CMD | MIO 21, FPGA Bank 500 |
| | SD_CD | MIO 24, FPGA Bank 500 |
|
|
RJ45 Connector
TE0802 is equipped with a RJ45 connector and an Ethernet PHYs. RJ45 connector J4 is connected to Ethernet PHYs U6.
| Scroll Title |
|---|
| anchor | Table_SIP_RJ45 |
|---|
| title | RJ45 Connector Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Pin | Schematic | ETH Pin | Notes |
|---|
| 2 | PHY_MDI0_P | MDIP[0] |
| | 3 | PHY_MDI0_N | MDIN[0] |
| | 4 | PHY_MDI1_P | MDIP[1] |
| | 5 | PHY_MDI1_N | MDIN[1] |
| | 6 | PHY_MDI2_P | MDIP[2] |
| | 7 | PHY_MDI2_N | MDIN[2] |
| | 8 | PHY_MDI3_P | MDIP[3] |
| | 9 | PHY_MDI3_N | MDIN[3] |
|
|
USBs Sockets
TE0802 is equipped with a Micro USB2.0 B connector J8 and a USB3.0 connector J11.
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| Scroll Title |
|---|
| anchor | Table_SIP_USB3 |
|---|
| title | USB3.0 A Socket Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| USB3.0 Pin | Schematic | Connected to | Notes |
|---|
| D- | USB0_D_N | USB PHY, U22 |
| | D+ | USB0_D_P | USB PHY, U22 |
| | StdA_SSRX- | USB_RX2_N | FPGA Bank 505 |
| | StdA_SSRX+ | USB_RX2_P | FPGA Bank 505 |
| | StdA_SSTX- | USB_TX2_N | FPGA Bank 505 |
| | StdA_SSTX+ | USB_TX2_P | FPGA Bank 505 |
| | VBUS | VBUS | USB PHY, U22 |
|
|
SSD M.2 Connector
TE0802 is equipped with a SSD M.2 connector (U5).
| Scroll Title |
|---|
| anchor | Table_SIP_SSD |
|---|
| title | SSD M.2 Connector Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Pin | Schematic | Connected to | Notes |
|---|
| PERn0/SATA-B+ | SSD_RX3_N | Pin M22, FPGA Bank 505 |
| | PERp0/SATA-B- | SSD_RX3_P | Pin M21, FPGA Bank 505 |
| | PERn0/SATA-A+ | SSD_TXC3_N | Pin K22, FPGA Bank 505 |
| | PERp0/SATA-A- | SSD_TXC3_P | Pin M21, FPGA Bank 505 |
| | REFCLKN | SSD_RCLK_N | Pin 9, Clock Generator U8 |
| | REFCLKP | SSD_RCLK_P | Pin 10, Clock Generator U8 |
| | DAS/DSS# | SSD_DAS | MIO35, FPGA Bank 501 |
| | DEVSLP | SSD_SLEEP | MIO32, FPGA Bank 501 |
| | PERST# | SSD_PERSTn | MIO31, FPGA Bank 501 |
| | CLKREQ# | SSD_CLKRQ | MIO33, FPGA Bank 501 |
| | PEWake# | SSD_WAKE | MIO34, FPGA Bank 501 |
|
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Display Port Connector
TE0802 is equipped with a Display Port connector (J3).
| Scroll Title |
|---|
| anchor | Table_SIP_DP |
|---|
| title | Display Port Socket Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic | Corresponding Signals | Connected to | Notes |
|---|
| DP_TX_L0_P/N | DP0_TX_P/N | Pin A19/A20, FPGA Bank 505 |
| | DP_TX_L1_P/N | DP1_TX_P/N | Pin C19/C20, FPGA Bank 505 |
| | DP_TX_AUX_P/N | DP_AUX_TX/RX | MIO27, MIO30, FPGA Bank 501 |
|
|
D-Sub Connector
TE0802 is equipped with a D-Sub connector (J7).
| Scroll Title |
|---|
| anchor | Table_SIP_VGA |
|---|
| title | D-Sub Connector Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic | Corresponding Signals | Connected to | Notes |
|---|
| VGA_RED | VGA_R0...3 | Bank 65 | Red Channel | | VGA_GREEN | VGA_G0...3 | Bank 65 | Green Channel | | VGA_BLUE | VGA_B0...3 | Bank 66 | Blue Channel | | VGA_RGB_HSYNC | VGA_HS | Bank 26 | Horizontal Sync | | VGA_RGB_VSYNC | VGA_VS | Bank 26 | Vertical Sync |
|
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Headphone Connector
TE0802 is equipped with a headphone connector (J12).
| Scroll Title |
|---|
| anchor | Table_SIP_HP |
|---|
| title | Headphone Connector Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic | Connected to | Notes |
|---|
| JACKSNS | Pin F3, FPGA Bank 65 |
| | PWM_R | Pin F4, FPGA Bank 65 |
| | PWM_L | Pin E3, FPGA Bank 65 |
|
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Grove Connector
TE0802 is equipped with a grove connector (J10).
| Scroll Title |
|---|
| anchor | Table_SIP_Grove |
|---|
| title | Grove Connector Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic | Connected to | Notes |
|---|
| Grove_SCL0 | MIO18, FPGA Bank 500 |
| | Grove_SDA0 | MIO19, FPGA Bank 500 |
|
|
Pmod Sockets
TE0802 has 2 Pmod 2x6 host sockets which are connected to the FPGA.
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| Scroll Title |
|---|
| anchor | Table_SIP_TestPoint |
|---|
| title | Test Points Information |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
Test Point | Signals | B2B Connector | Notes |
|---|
| 1 |
JB3-124 | | +1.1V_LPDDR4 | - |
| | 2 | +1.8V_MGTRAVTT | - |
| | 3 | +1.8V_PL | - |
| | 4 | FT_B_TX | - |
| | 5 | DP_TX_PWR | - |
| | 6 | GND | - |
| | 7 | GND | - |
| | 8 | PMIC2_SDA | - |
| | 9 | PMIC2_TP | - |
| | 10 | ONKEY2 | - |
| | 11 | PMIC2_SCL | - |
| | 12 | DP_TX_HPD | - |
| | 13 | DP_TX_PWR | - |
| | 14 | INT_SCL1 | - |
| | 15 | INT_SDA1 | - |
| | 16 | FT_B_RX | - |
| | 17 | CLOCKDIST_OE | - |
| | 18 | +0.85V_VCCINT | - |
| | 19 | +3.3V | - |
| | 20 | +1.8V_PS | - |
| | 21 | ERR_STATUS | - |
| | 22 | +1.2V_PSPLL | - |
| | 23 | GND | - |
| | 24 | GND | - |
| | 25 | PMIC1_SCA | - |
| | 26 | PMIC1_SDA | - |
| | 27 | ONKEY1 | - |
| | 28 | PMIC1_TP | - |
| | 29 | POR_B | - |
| | 30 | PSBATT | - |
| | 31 | SRST_B | - |
| | 32 | DONE | - |
| | 33 | INIT_B | - |
| | 34 | VBUS | - |
| | 35 | USB_VBUS | - |
| | 36 | PROG_B | - |
| | 37 | ERR_OUT |
2 | JB1-22 | 3 | JB1-34 | 4 | JB1-36 | 5 | JB1-24 | 6 | JB3-81 | 7 | JB3-88 | 8 | JB3-87 | 9 | JB3-82 | 10 | JB3-141 | 11 | JB3-148 | 12 | JB3-147 | 13 | JB3-142 | 14 | JB1-165...168 | 15 | - | 16 | JB1-147...148 | 17-18
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On-board Peripherals
| Page properties |
|---|
|
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
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| Scroll Title |
|---|
| anchor | Table_PWR_PR |
|---|
| title | Module Power Rails |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Power Rail Name | Direction | Notes |
|---|
| VIN | InIN | Supply Voltage | | +5V | Out | J1...2 | | +3.3V | Out | J14, J10 |
|
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