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anchor	Figure_OV_BD
title	TEBA0714 block diagram

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draw.io Diagram

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anchor	Figure_OV_MC
title	TEBA0714 main components

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draw.io Diagram

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6-pin header J26 for selecting PL-bank I/O voltage
6-pin header J27 for selecting XMOD/JTAG VCCIO
Samtec Razor Beam™ LSHM-150 B2B connector, JM1
Samtec Razor Beam™ LSHM-150 B2B connector, JM2
XMOD header, JX1
Ultra small SMT coaxial connector, J5
Ultra small SMT coaxial connector, J6
Ultra small SMT coaxial connector, J7
Ultra small SMT coaxial connector, J8
User LED D1 (green)
User LED D2 (red)
LED D3 (red) indicating FPGA's 'Programming DONE'-signal
SFP+ Connector, J1
10-pin header solder pads J4 for access to SoM's PL I/O-banks (LVDS pairs possible)
16-pin header solder pads J3, JTAG/UART header with ADC and MGT clock input
50-pin header solder pads J20 for access to SoM's PL I/O-banks (LVDS pairs possible)
50-pin header solder pads J17 for access to SoM's PL I/O-banks (LVDS pairs possible)

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

VCCIO voltage selection jumpers are all set to 1.8 V.
Pin headers (not soldered to the board, but included in the package as separate component)

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anchor	Table_OV_IDS
title	Initial delivery state of programmable devices on the module

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System Controller CPLD

Storage device name	Content	Notes
Quad SPI Flash-	EEPROM	DDR3 SDRAM	-	-

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