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anchor	Figure_OV_BD
title	TEBA0714 block diagram

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draw.io Diagram

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anchor	Figure_OV_MC
title	TEBA0714 main components

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draw.io Diagram

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6-pin header J26 for selecting PL-bank I/O voltage
6-pin header J27 for selecting XMOD/JTAG VCCIO
Samtec Razor Beam™ LSHM-150 B2B connector, JM1
Samtec Razor Beam™ LSHM-150 B2B connector, JM2
XMOD header, JX1
Voltage Regulator, U1
User Red LED D2
User Green LED D1 (red)
SFP+ Connector, J1
Red LED D3, indicating FPGA's 'Programming DONE'-signal
1050-pin header solder pads J4 J20 for access to SoM's PL I/O-banks (LVDS pairs possible)
16-pin header solder pads J3, JTAG/UART header with ADC and MGT clock input
5010-pin header solder pads J20 J4 for access to SoM's PL I/O-banks (LVDS pairs possible)
50-pin header solder pads J17 for access to SoM's PL I/O-banks (LVDS pairs possible)

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anchor	Table_OV_BP
title	Boot process.

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Signal	MODE Signal State	Boot Mode	Note
BOOTMODE	high or open	Master SPI, x4 Mode
BOOTMODE	low or ground	Slave Selects MAP

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anchor	Table_OV_RST
title	Reset process.

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Signal	B2B

I/O

Signal State	Note
PROG_B	JM1-94	Active Low	Clear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge).

Note

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