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The PCIexpress signal "PERST#" is forwarded to the SoM using RGPIO port:  rgpio_in_data_i(11) <= PCIE_PERST;signal CPLD_IO_1 (corresponding to B2B pin JB1-88).

      CPLD_IO_1 <= (PCIE_PERST and M3_3VOUT); -- forward PCIE PERST# to SOM

As long as RGPIO is not enabled, LED1 shows the inverted status of the PCIE_PERST signal (See USR LED).

JTAG MUX

The folowing table summarizes the JTAG MUX. Only FMC and SoM JTAG have to be handled in the CPLD explicitly. Discrimination between Module CPLD and Module SOC/FPGA are done via hard connected dip switch. Same is true for TEF1002 CPLD MAX10.

Module control

The module control signals are connected to dip switches:

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LED1 <= rgpio_out_data_i(19) when soc_rgpio_active='1' else Not(PCIE_PERST);LED2 <= rgpio_out_data_i(18) when soc_rgpio_active='1' else '0';

PCIe PERST#

PCIe Reset signal is forwarded to the B2B pin JB1-88. As long as RGPIO is not enabled, LED 1 shows the inverted status of the PCIE_PERST signal.

1' else Not(PCIE_PERST);

LED2 <= rgpio_out_data_i(18) when soc_rgpio_active='1' else '0';      CPLD_IO_1 <= PCIE_PERST; -- forward PCIE PERST# to SOM

Appx. A: Change History and Legal Notices

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