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When RGPIO is aktive the FF resets are driven low via rgpio_out_data_i(23).

For FF I2C see I2C chapter. Module Present and Interrupt signals are forwarded to SoM via RGPIO ports:

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The PCIexpress signal "PERST#" is forwarded to the SoM using signal CPLD_IO_1 (corresponding to B2B pin JB1-88.As long as RGPIO is not enabled, LED1 shows the inverted status of the PCIE_PERST signal (See USR LED).

      CPLD_IO_1 <= (PCIE_PERST and M3_3VOUT); -- forward PCIE PERST# to SOM

As long as RGPIO is not enabled, LED1 shows the inverted status of the PCIE_PERST signal (See USR LED).

JTAG MUX

The folowing table summarizes the JTAG MUX. Only FMC and SoM JTAG have to be handled in the CPLD explicitly. Discrimination between Module CPLD and Module SOC/FPGA are done via hard connected dip switch. Same is true for TEF1002 CPLD MAX10.

Module control

The module control signals are connected to dip switches:

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