Versions Compared

Old Version 4

changes.mady.by.user Martin Rohrmüller

Saved on

compared with

New Version Current

changes.mady.by.user Martin Rohrmüller

Saved on

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Feature Summary

  • Power Management
    • SATA pin 7 power control
  • Status LED
  • FMC VADJ Power
  • SFP control
  • FFA & FFB control
  • JTAG MUX
  • Module control
  • RESET
  • I2C MUX
  • PHY LEDs
  • RGPIO
  • USR LED

...

M_
Scroll Title
anchorTable_SC_Ports
titleSC CPLD ports

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

VHDL Port nameDirectionSC CPLD PinConnected toFunctionNotes
ACBUS0
A4FTDI U4, pin 22GPIO's available to user











currently not used/implemented

(FIFO or other FTDI functions when FTDI reprogrammed)











ACBUS1
B4FTDI U4, pin 23
ACBUS2
A5FTDI U4, pin 24
ACBUS3
B5FTDI U4, pin 25
ACBUS4
A6FTDI U4, pin 26
ACBUS5
B6FTDI U4, pin 27
ACBUS6
A7FTDI U4, pin 28
ACBUS7
A8FTDI U4, pin 29
ADBUS4
A2FTDI U4, pin 17
ADBUS5
B2FTDI U4, pin 18
ADBUS6
A3FTDI U4, pin 19
ADBUS7
B3FTDI U4, pin 20
P_TCKING2
FTDI U4
J5, pin
12
1
Forwarded (FIFO or other FTDI functions when FTDI reprogrammed)
JTAG signals from
FTDI chip. Signal names: TCK, TDI, TDO, TMS
pin header J5 for SC CPLD programming (S2-4 ON)



Can be used as additional IOs via JTAG pinsharing, JTAGEN (S2-4 OFF). Schematic signal names without 'P_'.



P_TDIINF5
FTDI U4
J5, pin
13
9
P_TDOOUTF6
FTDI U4
J5, pin
14
3
P_TMSING1
FTDI U4
J5, pin
15
5
M
F_TCK
OUT
IN
H5
H2
JB2
FTDI U4, pin
100
12
4x5 Module JTAG
Forwarded JTAG signals from FTDI chip. Signal names: TCK, TDI, TDO, TMS(FIFO or other FTDI functions when FTDI reprogrammed)
F_TDIING4FTDI U4, pin 13
F_TDOOUTF4FTDI U4, pin 14
F_TMSINH5FTDI U4, pin 15
M_TCKOUTH5JB2, pin 1004x5 Module JTAG



Bank with VCCIO is VREF_JTAG from Module



M_TDIOUTJ2JB2, pin 96
M_
Bank with VCCIO is VREF_JTAG from Module
M_TDIOUTJ2JB2, pin 96
TDOINJ1JB2, pin 98
M_TMSOUTH6JB2, pin 94
FMC_TCKOUTF8J1, pin D29FMC JTAG




TRST not used



FMC_TDIOUTM7J1, pin D30
FMC_TDOINN7J1, pin D31
FMC_TMSOUTM8J1, pin D33
FMC_TRST
N8J1, pin D34
PCIE_TCK
L11J3, pin A5PCIe JTAG




Currently not used




PCIE_TDI
N12J3, pin A6
PCIE_TDO
M12J3, pin A7
PCIE_TMS
M13J3, pin A8
PCIE_TRST
G10J3, pin B9
PCIE_PERSTINF12J3, pin A11Indication that PCIe Bus is up (power, clocks)
EN_FMCOUTL4U14, pin 9Enable switched 3.3V FMC powerpulled down
EN_FMC_VADJOUTK7U1, pin 41Enable IO power FMC_VADJpulled down
EN_PEROUTF13Q4, pin 5Enable perepherie power 3V3_PERpulled down
FAN_FMC_ENOUTK8Q1, pin 5Enable FMC FANfloating during configuration (no pull down)
FMC_PG_C2MOUTM5J1, pin D1Indicate that all FMC related powers are uppulled up
FMC_PRSNT_M2C_LINE9J1, pin H2Indicate if FMC installedLow when FMC present, CPLD weak pullup enabled
FMC_SCLOUTJ8J1, pin C31I2C 2-wire serial busMUX in CPLD
FMC_SDAINOUTF9J1, pin C30
PG_FMC_VADJINJ6U1, pin 35Indicate FMC VADJ power is up
FF_RSTLOUTB9J13, pin 6  and J18, pin 6Reset configurationBoth FF are resetted simultanously when pulled LOW
FFA_INTLINE8J13, pin 5Indicate interrrupt

LOW when fault condition, pulled up

FFA_MPRSINC10J13, pin 3Indicate FF Module installedLOW when Module present, pulled up
FFA_MSELOUTC9J13, pin 4Select attached FF ModulePull low to use I2C
FFA_SCLOUTD6J13, pin 8I2C 2-wire serial busMUX in CPLD
FFA_SDAINOUTE6J13, pin 7
FFB_INTLINA10J18, pin 5Indicate interrruptLOW when fault condition, pulled up
FFB_MPRSINA11J18, pin 3Indicate FF Module installedLOW when Module present, pulled up
FFB_MSELOUTB10J18, pin 4Select attached FF ModulePull low to use I2C
FFB_SCLOUTD8J18, pin 8I2C 2-wire serial busMUX in CPLD
FFB_SDAINOUTA9J18, pin 7
CPLD_IO_1INB12JB1, pin 88(M)IOs from 4x5 Module(M)IOs used for ETH PHY LEDs

CPLD_IO_2INA12JB1, pin 92(M)IOs from 4x5 Module
M10_RST
D1

TP22




Not used


M10_RX
E4TP24
M10_TX
E3TP23
EN1OUTD11JB1, pin 27Enable on module powerDepends on module, on some similar to reset.
MODEOUTB11JB1, pin 31Boot Mode selectionFor Zynq modules only. (LOW → SD, HIGH → primary QSPI)
NOSEQOUTE13JB1, pin 8Disable module CPLD power managementDepends on module. On some modules no extended CPLD power management avaialble.
PGOODINOUTC11JB1, pin 29Power good signal

This is only for monitoring, do not use as powerenable! Pulled up.

RESINOUTE12JB2, pin 17Module ResetAktive LOW
M3.3VOUTINM4JB2, pin 9 and 11Indicates module power is up

Used for perepherie power enable. Floating when no module installed (no pull down).

SFPA_LOSINM10J12, pin 8SFP signal lossHIGH indicates signal loss
SFPA_M-DEF0INF10J12, pin 6SFP modul absentHIGH when module physically absent
SFPA_RS0OUTN10J12, pin 7SFP rate select RXLOW for 1000BASE-SX, HIGH for 10GBASE-SR
SFPA_RS1OUTM11J12, pin 9SFP rate select TXLOW for 1000BASE-SX, HIGH for 10GBASE-SR
SFPA_SCLOUTL10J12, pin 5I2C 2-wire serial busMUX in CPLD
SFPA_SDAINOUTN9J12, pin 4
SFPA_TX_DISOUTM9J12, pin 3SFP transmitter disableHIGH disables transmitter
SFPA_TX_FAULTING9J12, pin 2Indicates SFP laser faultHIGH indicates fault
VID0_FMC_VADJOUTE10U1, pin 34FMC_VADJ Voltage selectChip internal pulled up


VID1_FMC_VADJOUTJ7U1, pin 33
VID2_FMC_VADJOUTL5U1, pin 32
VID0INK6S2-1For FMC_VADJ Voltage select





VID1INN5S2-2
VID2INN4S2-3
FMC_JTAGINL3S2-6Select FMC JTAG port
CM0INM3S2-7SoM enable power
CM1INL2S2-8SoM Bootmode
CM2INK2S3-1disable SoM pwersequenzing
USR0INK1S3-2FMC VADJ power enablealso if no FMC installed
USB_OCIND9U12, pin 5

EN_5VSATAOUTE1U15, pin 1Enable/Disable SATA pin 7 power
OC_VSATAINF1U15, pin 2Overcurrent detection SATA pin 7 power
BUTTONINN6S1Module reset button
SD-CDINM1J8, pin 9SD-Card card detect switchCurrently not used
LED1OUTJ5D1user LED
LED2OUTK5D2
LED_D4OUTC2D4Status LED
PHY_LED1OUTD12J9Phy LEDs







PHY_LED1ROUTC13J9
PHY_LED2OUTB13J9
PHY_LED2ROUTC12J9
A_00_NINJ10JB1, pin 38SDA IN "three wire" I2C
A_00_PINK10JB1, pin 36SCL IN"three wire" I2C
A_01_NOUTL12JB1, pin 35TX dataRGPIO
A_01_POUTK11JB1, pin 37SDA OUT"three wire" I2C
A_02_NINJ12JB1, pin 41RX CLKRGPIO
A_02_PINK12JB1, pin 39RX dataRGPIO
A_03_N
H10JB1, pin 44Module to CPLD communicationcurrently not used
A_03_P
J9JB1, pin 42
A_04_N
H13JB1, pin 47
A_04_P
J13JB1, pin 45
A_05_
N
PIN
H8
H9JB1, pin
57
55
A_05_
P
NIN
H9
H8JB1, pin
55
57PHY LEDsHave to be Forwarede on SoM to this pins.
A_06_PING13JB1, pin 51
A_06_NING12JB1, pin 49I2C GPIO MUX 0I2C MUX also used for FireFlys MSEL
A_07INL13JB1, pin 34I2C GPIO MUX 1


Functional Description

Power Management

The M3_3VOUT rail of the attached SoM is used to power up all the powerrails etc on TEF1002. further dependencies ar given in the table below:

To Do ...

Scroll Title
anchorTable_power_management
titlePower Management
RGPIO not aktive

...


Port/Signaldepends on (RGPIO not aktive)additional when RGPIO aktiveDescriptionRemark
EN_PERM3_3VOUT

...

rgpio_out_data_i(

...

15)Enable perepherie power 3V3_PERvia PWR_EN_Signal
FMC_PWR_setM3_3VOUT

...

rgpio_out_data_i(16)Signal indicate FMC enable
EN_FMCFMC_PWR_set and NOT(FMC_PRSNT_M2C_L)

...

...

rgpio_out_data_i(

...

17)Enable switched 3.3V FMC power
FAN_FMC_EN

...

FMC_PWR_set and NOT(FMC_PRSNT_M2C_L)

...

 -Enable FMC FAN
EN_FMC_VADJ

...

(FMC_PWR_set and NOT(FMC_PRSNT_M2C_L)) or (USR0 and FMC_PRSNT_

...

M2C_

...

L)-Enable IO power FMC_VADJUSR0 dip switch S3-2 can be used to enable FMC_VADJ when no FMC installed
EN5VSATA

if((OC_VSATA = '0') or (OC_SATA_DISABLED = '1'))then
   EN5VSATA <= '0';
   OC_SATA_DISABLED <= '1';
else
   EN5VSATA <= M3_3VOUT;
end if;

-Enable  5V SATA on pin 7Implemented with latch, when disabled, will be disabled until board power cycle.
FMC_PG_C2MFMC_PWR_set and NOT(FMC_PRSNT_M2C_L) and PG_FMC_VADJ-Indicate that all FMC related powers are up

FMC_PG_C2M <= (PG_FMC_VADJ and M3_3VOUT);

--Perepherie power, Enable Power for SFP and FireFly

PWR_EN_Signal <= rgpio_out_data_i(15) and M3_3VOUT when soc_rgpio_active='1' else M3_3VOUT;

...



Status LED

The Status LED D4 is utilized in the following way:

Scroll Title
anchorTable_LED_Status
titleStatus LED description


Sequenz
Description
*ooooooo1 times fast blink with a breakSOM PGOOD fail
**oooooo2 times fast blink with a breaknot used
***ooooo3 times fast blink with a breakFMC power Error
****oooo4 times fast blink with a break
not used
SATA pin 7 overcurrent ERROR
*****ooo5 times fast blink with a breakUSB Power Error
******oo6 times fast blink with a breakFirefly A or B Error
*******o7 times fast blink with a breakSFPA_TX_FAULT or SFPA_LOS
ONLED ONAll OK


FMC VADJ Power

Three of the dip switches are linked to the voltage selection signals of FMC_VADJ:

...

The PCIexpress signal "PERST#" is forwarded to the SoM using RGPIO port:  rgpio_in_data_i(11) <= PCIE_PERST;is forwarded to the SoM using signal CPLD_IO_1 (corresponding to B2B pin JB1-88).

      CPLD_IO_1 <= (PCIE_PERST and M3_3VOUT); -- forward PCIE PERST# to SOM

As long as RGPIO is not enabled, LED1 shows the inverted status of the PCIE_PERST signal (See USR LED).

JTAG MUX

The folowing table summarizes the JTAG MUX. Only FMC and SoM JTAG have to be handled in the CPLD explicitly. Discrimination between Module CPLD and Module SOC/FPGA are done via hard connected dip switch. Same is true for TEF1002 CPLD MAX10.

Scroll Title
anchorTable_JTAG
titleJTAG selection

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

ON
SignalJTAGEN S2-4M_JTAGEN S2-5FMC_JTAG S2-6
CPLD MAX 10 (header J5)

OFFON

DNCXDNCX
4x5 SoM CPLD (micro USB J10)OFFONOFFOFF
4x5 SoC/FPGA ON(micro USB J10)OFFOFFOFF
FMC (micro USB J10)OFFFMCONDNCXON


Module control

The module control signals are connected to dip switches:

...

Scroll Title
anchorTable_I2C_SoM
titleConnection I2C to SoM

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

deviceSELNotes
SFPA00
FMC01
FFA10also used for FFA_MSEL
FFB11also used for FFB_MSEL


A "three wire" I2C interface is used to connect the CPLD I2C  to the SoM:

Scroll Title
anchorTable_I2C_SoM
titleConnection I2C to SoM

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

VHDL Port nameDirectionSC CPLD PinConnected toFunctionNotes
A_00_NINJ10JB1, pin 38SDA IN "three wire" I2C
A_00_PINK10JB1, pin 36SCL IN"three wire" I2C
A_01_POUTK11JB1, pin 37SDA OUT"three wire" I2C


The devices SDA are driven in the following way: DEVICE_XY_SDA <= '0' when SEL= "XY" and A_00_N='0' else 'Z';

...

Scroll Title
anchorTable_SC_I2C_MUX
titleSC I2C MUX ports

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

VHDL Port nameDirectionSC CPLD PinConnected toFunctionNotes
FMC_SCLOUTJ8J1, pin C31I2C 2-wire serial busMUX in CPLD
FMC_SDAINOUTF9J1, pin C30
FFA_MSELOUTC9J13, pin 4Select attached FF ModulePull low to use I2C
FFA_SCLOUTD6J13, pin 8I2C 2-wire serial busMUX in CPLD
FFA_SDAINOUTE6J13, pin 7
FFB_MSELOUTB10J18, pin 4Select attached FF ModulePull low to use I2C
FFB_SCLOUTD8J18, pin 8I2C 2-wire serial busMUX in CPLD
FFB_SDAINOUTA9J18, pin 7
A_01_POUTK11JB1, pin 37SDA OUT"three wire" I2C
A_06_NING12JB1, pin 49I2C GPIO MUX 0I2C MUX also used for FireFlys MSEL
A_07INL13JB1, pin 34I2C GPIO MUX 1


PHY LEDs

As soon as the module M3_3VOUT is ready the The following signals are used to drive the PHY LEDs.

Scroll Title
anchorTable_PHY_LEDs
titleConnection of PHY LEDs

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal VHDLnameFunctionNotes
CPLDA_IO05_1NPHY_LED1drive LEDConnected to JB1-8857
net_gndPHY_LED1Rselect coloryellow
CPLDA_IO06_2PPHY_LED2drive LEDConnected to JB1-9251
net_gndPHY_LED2Rselect colorgreen


...

Low when FMC present
Scroll Title
anchorTable_RGPIO
titleSignals handeld by RGPIO

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue
1
sortEnabledfalse
cellHighlightingtrue

Signal VHDLnameFunctionNotes
SoC write (23)FF_RSTLReset configurationBoth FF are resetted simultanously when pulled LOW
SoC write (22)SFPA_TX_DISSFP transmitter disableHIGH disables transmitter
SoC write (21)SFPA_RS0SFP rate select RXLOW for 1000BASE-SX, HIGH for 10GBASE-SR
SoC write (20)SFPA_RS1SFP rate select TXLOW for 1000BASE-SX, HIGH for 10GBASE-SR
SoC write (19)LED1user LEDs
SoC write (18)LED2
SoC write (17)EN_FMCEnable switched 3.3V FMC powerpulled down
Signal VHDLnameFunctionNotes
SOC read (11)PCIE_PERSTIndication that PCIe Bus is up (power, clocks)
SoC write (17)EN_FMCEnable switched 3.3V FMC powerpulled down
SoC write (15)PWR_EN_SignalEnable perepherie power 3V3_PERused for EN_PER
SOC read (15)FMC_PRSNT_M2C_LIndicate if FMC installed
SoC write (16)FMC_PWR_setTurn on FMC Powerused for EN_FMC_VADJ and FAN_FMC_EN
SOC read
SoC write (
14
15)
PG
PWR_
FMC
EN_
VADJ
SignalEnable perepherie power 3V3_PERused for EN_PER
Indicate FMC VADJ power is upSoC write (23)FF_RSTLReset configurationBoth FF are resetted simultanously when pulled LOW
SOC read (
21
23)FFA_
INTL
MPRSIndicate
interrrupt
FF Module installedLOW when
fault condition
Module present, pulled up
SOC read (
13
22)
FFA
FFB_MPRSIndicate FF Module installedLOW when Module present, pulled up
SOC read (
20
21)
FFB
FFA_INTLIndicate interrrupt

LOW when fault condition, pulled up

SOC read (
22
20)FFB_
MPRS
INTLIndicate
FF Module installed
interrruptLOW when
Module present
fault condition, pulled up
SOC read (
17
19)SFPA_
LOS
TX_FAULTIndicates SFP
signal loss
laser faultHIGH indicates
signal loss
fault
SOC read (18)SFPA_M-DEF0SFP modul absentHIGH when module physically absent
SoC write
SOC read (
21
17)SFPA_
RS0
LOSSFP
rate select RXLOW for 1000BASE-SX, HIGH for 10GBASE-SRSoC write (20)SFPA_RS1SFP rate select TXLOW for 1000BASE-SX, HIGH for 10GBASE-SRSoC write (22)SFPA_TX_DISSFP transmitter disableHIGH disables transmitterSOC read (19)SFPA_TX_FAULTIndicates SFP laser faultHIGH indicates fault
signal lossHIGH indicates signal loss
SOC read (16)SDCDSD card detectLow when card inserted
SOC read (15)FMC_PRSNT_M2C_LIndicate if FMC installedLow when FMC present
SOC read (14)PG_FMC_VADJIndicate FMC VADJ power is up
SOC read (13)OC_VSATAIndicate SATA pin 7 overcurrent
SOC read (12)USB_OCIndicate USB overcurrent
SoC write (19)LED1user LEDsSoC write (18)LED2



Scroll Title
anchorTable_RGPIO_SoM
titleConnection RGPIO to SoM

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

VHDL Port nameDirectionSC CPLD PinConnected toFunctionNotes
A_01_NOUTL12JB1, pin 35TX data
A_02_NINJ12JB1, pin 41RX CLK
A_02_PINK12JB1, pin 39RX data


USR LED

User LEDs are accesible via RGPIO:

Scroll Title
anchorTable_User_LEDs
titleConnection of User LEDs

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Signal VHDLnameFunctionNotes
SoC write(19)LED1-user defined
SoC write(18)LED2-user defined
SoC write(19)LED1-user defined
SoC write(18)LED2-user defined


LED1 <= rgpio_out_data_i(19) when soc_rgpio_active='1' else Not(PCIE_PERST);

LED2 <= rgpio_out_data_i(18) when soc_rgpio_active='1' else '0';

Appx. A: Change History and Legal Notices

...

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
current-version
current-version
prefixv.

REV01REV03REV01REV02

Page info
modified-user
modified-user

Clearified PCIe PERST#

v.14

REV03REV02

Martin Rohrmüller

initial version

All

Page info
modified-users
modified-users


...