Page History

...

Feature Summary

Power Management
- SATA pin 7 power control
Status LED
FMC VADJ Power
SFP control
FFA & FFB control
JTAG MUX
Module control
SATA pin 7 power control
RESET
I²C MUX
PHY LEDs
RGPIO
USR LED

...

Scroll Title

anchor	Table_SC_Ports
title	SC CPLD ports

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

VHDL Port name	Direction	SC CPLD Pin	Connected to	Function	Notes
ACBUS0		A4	FTDI U4, pin 22	GPIO's available to user	currently not used/implemented (FIFO or other FTDI functions when FTDI reprogrammed)
ACBUS1		B4	FTDI U4, pin 23
ACBUS2		A5	FTDI U4, pin 24
ACBUS3		B5	FTDI U4, pin 25
ACBUS4		A6	FTDI U4, pin 26
ACBUS5		B6	FTDI U4, pin 27
ACBUS6		A7	FTDI U4, pin 28
ACBUS7		A8	FTDI U4, pin 29
ADBUS4		A2	FTDI U4, pin 17
ADBUS5		B2	FTDI U4, pin 18
ADBUS6		A3	FTDI U4, pin 19
ADBUS7		B3	FTDI U4, pin 20
P_TCK	IN	G2	J5, pin 1	JTAG signals from pin header J5 for SC CPLD programming (S2-4 ON)	Can be used as additional IOs via JTAG pinsharing, JTAGEN (S2-4 OFF). Schematic signal names without 'P_'.
P_TDI	IN	F5	J5, pin 9
P_TDO	OUT	F6	J5, pin 3
P_TMS	IN	G1	J5, pin 5
F_TCK	IN	H2	FTDI U4, pin 12	Forwarded JTAG signals from FTDI chip. Signal names: TCK, TDI, TDO, TMS	(FIFO or other FTDI functions when FTDI reprogrammed)
F_TDI	IN	G4	FTDI U4, pin 13
F_TDO	OUT	F4	FTDI U4, pin 14
F_TMS	IN	H5	FTDI U4, pin 15
M_TCK	OUT	H5	JB2, pin 100	4x5 Module JTAG	Bank with VCCIO is VREF_JTAG from Module
M_TDI	OUT	J2	JB2, pin 96
M_TDO	IN	J1	JB2, pin 98
M_TMS	OUT	H6	JB2, pin 94
FMC_TCK	OUT	F8	J1, pin D29	FMC JTAG	TRST not used
FMC_TDI	OUT	M7	J1, pin D30
FMC_TDO	IN	N7	J1, pin D31
FMC_TMS	OUT	M8	J1, pin D33
FMC_TRST		N8	J1, pin D34
PCIE_TCK		L11	J3, pin A5	PCIe JTAG	Currently not used
PCIE_TDI		N12	J3, pin A6
PCIE_TDO		M12	J3, pin A7
PCIE_TMS		M13	J3, pin A8
PCIE_TRST		G10	J3, pin B9
PCIE_PERST	IN	F12	J3, pin A11	Indication that PCIe Bus is up (power, clocks)
EN_FMC	OUT	L4	U14, pin 9	Enable switched 3.3V FMC power	pulled down
EN_FMC_VADJ	OUT	K7	U1, pin 41	Enable IO power FMC_VADJ	pulled down
EN_PER	OUT	F13	Q4, pin 5	Enable perepherie power 3V3_PER	pulled down
FAN_FMC_EN	OUT	K8	Q1, pin 5	Enable FMC FAN	floating during configuration (no pull down)
FMC_PG_C2M	OUT	M5	J1, pin D1	Indicate that all FMC related powers are up	pulled up
FMC_PRSNT_M2C_L	IN	E9	J1, pin H2	Indicate if FMC installed	Low when FMC present, CPLD weak pullup enabled
FMC_SCL	OUT	J8	J1, pin C31	I²C 2-wire serial bus	MUX in CPLD
FMC_SDA	INOUT	F9	J1, pin C30	I²C 2-wire serial bus	MUX in CPLD
PG_FMC_VADJ	IN	J6	U1, pin 35	Indicate FMC VADJ power is up
FF_RSTL	OUT	B9	J13, pin 6 and J18, pin 6	Reset configuration	Both FF are resetted simultanously when pulled LOW
FFA_INTL	IN	E8	J13, pin 5	Indicate interrrupt	LOW when fault condition, pulled up
FFA_MPRS	IN	C10	J13, pin 3	Indicate FF Module installed	LOW when Module present, pulled up
FFA_MSEL	OUT	C9	J13, pin 4	Select attached FF Module	Pull low to use I²C
FFA_SCL	OUT	D6	J13, pin 8	I²C 2-wire serial bus	MUX in CPLD
FFA_SDA	INOUT	E6	J13, pin 7	I²C 2-wire serial bus	MUX in CPLD
FFB_INTL	IN	A10	J18, pin 5	Indicate interrrupt	LOW when fault condition, pulled up
FFB_MPRS	IN	A11	J18, pin 3	Indicate FF Module installed	LOW when Module present, pulled up
FFB_MSEL	OUT	B10	J18, pin 4	Select attached FF Module	Pull low to use I²C
FFB_SCL	OUT	D8	J18, pin 8	I²C 2-wire serial bus	MUX in CPLD
FFB_SDA	INOUT	A9	J18, pin 7	I²C 2-wire serial bus	MUX in CPLD
CPLD_IO_1	IN	B12	JB1, pin 88	(M)IOs from 4x5 Module	(M)IOs used for ETH PHY LEDs
CPLD_IO_2	IN	A12	JB1, pin 92	(M)IOs from 4x5 Module	(M)IOs used for ETH PHY LEDs
M10_RST		D1	TP22		Not used
M10_RX		E4	TP24
M10_TX		E3	TP23
EN1	OUT	D11	JB1, pin 27	Enable on module power	Depends on module, on some similar to reset.
MODE	OUT	B11	JB1, pin 31	Boot Mode selection	For Zynq modules only. (LOW → SD, HIGH → primary QSPI)
NOSEQ	OUT	E13	JB1, pin 8	Disable module CPLD power management	Depends on module. On some modules no extended CPLD power management avaialble.
PGOOD	INOUT	C11	JB1, pin 29	Power good signal	This is only for monitoring, do not use as powerenable! Pulled up.
RESIN	OUT	E12	JB2, pin 17	Module Reset	Aktive LOW
M3.3VOUT	IN	M4	JB2, pin 9 and 11	Indicates module power is up	Used for perepherie power enable. Floating when no module installed (no pull down).
SFPA_LOS	IN	M10	J12, pin 8	SFP signal loss	HIGH indicates signal loss
SFPA_M-DEF0	IN	F10	J12, pin 6	SFP modul absent	HIGH when module physically absent
SFPA_RS0	OUT	N10	J12, pin 7	SFP rate select RX	LOW for 1000BASE-SX, HIGH for 10GBASE-SR
SFPA_RS1	OUT	M11	J12, pin 9	SFP rate select TX	LOW for 1000BASE-SX, HIGH for 10GBASE-SR
SFPA_SCL	OUT	L10	J12, pin 5	I²C 2-wire serial bus	MUX in CPLD
SFPA_SDA	INOUT	N9	J12, pin 4	I²C 2-wire serial bus	MUX in CPLD
SFPA_TX_DIS	OUT	M9	J12, pin 3	SFP transmitter disable	HIGH disables transmitter
SFPA_TX_FAULT	IN	G9	J12, pin 2	Indicates SFP laser fault	HIGH indicates fault
VID0_FMC_VADJ	OUT	E10	U1, pin 34	FMC_VADJ Voltage select	Chip internal pulled up
VID1_FMC_VADJ	OUT	J7	U1, pin 33
VID2_FMC_VADJ	OUT	L5	U1, pin 32
VID0	IN	K6	S2-1	For FMC_VADJ Voltage select
VID1	IN	N5	S2-2
VID2	IN	N4	S2-3
FMC_JTAG	IN	L3	S2-6	Select FMC JTAG port
CM0	IN	M3	S2-7	SoM enable power
CM1	IN	L2	S2-8	SoM Bootmode
CM2	IN	K2	S3-1	disable SoM pwersequenzing
USR0	IN	K1	S3-2	FMC VADJ power enable	also if no FMC installed
USB_OC	IN	D9	U12, pin 5
EN_5VSATA	OUT	E1	U15, pin 1	Enable/Disable SATA pin 7 power
OC_VSATA	IN	F1	U15, pin 2	Overcurrent detection SATA pin 7 power
BUTTON	IN	N6	S1	Module reset button
SD-CD	IN	M1	J8, pin 9	SD-Card card detect switch	Currently not used
LED1	OUT	J5	D1	user LED
LED2	OUT	K5	D2	user LED
LED_D4	OUT	C2	D4	Status LED
PHY_LED1	OUT	D12	J9	Phy LEDs
PHY_LED1R	OUT	C13	J9
PHY_LED2	OUT	B13	J9
PHY_LED2R	OUT	C12	J9
A_00_N	IN	J10	JB1, pin 38	SDA IN	"three wire" I²C
A_00_P	IN	K10	JB1, pin 36	SCL IN	"three wire" I²C
A_01_N	OUT	L12	JB1, pin 35	TX data	RGPIO
A_01_P	OUT	K11	JB1, pin 37	SDA OUT	"three wire" I²C
A_02_N	IN	J12	JB1, pin 41	RX CLK	RGPIO
A_02_P	IN	K12	JB1, pin 39	RX data	RGPIO
A_03_N		H10	JB1, pin 44	Module to CPLD communication	currently not used
A_03_P		J9	JB1, pin 42
A_04_N		H13	JB1, pin 47
A_04_P		J13	JB1, pin 45
A_05_NP	IN	H8H9	JB1, pin 5755
A_05_PN	IN	H9H8	JB1, pin 5557	PHY LEDs	Have to be Forwarede on SoM to this pins.
A_06_P	IN	G13	JB1, pin 51	PHY LEDs	Have to be Forwarede on SoM to this pins.
A_06_N	IN	G12	JB1, pin 49	I2C GPIO MUX 0	I2C MUX also used for FireFlys MSEL
A_07	IN	L13	JB1, pin 34	I2C GPIO MUX 1	I2C MUX also used for FireFlys MSEL

...

The PCIexpress signal "PERST#" is forwarded to the SoM using RGPIO port: rgpio_in_data_i(11) <= PCIE_PERST;signal CPLD_IO_1 (corresponding to B2B pin JB1-88).

CPLD_IO_1 <= (PCIE_PERST and M3_3VOUT); -- forward PCIE PERST# to SOM

As long as RGPIO is not enabled, LED1 shows the inverted status of the PCIE_PERST signal (See USR LED).

JTAG MUX

The folowing table summarizes the JTAG MUX. Only FMC and SoM JTAG have to be handled in the CPLD explicitly. Discrimination between Module CPLD and Module SOC/FPGA are done via hard connected dip switch. Same is true for TEF1002 CPLD MAX10.

Scroll Title

anchor	Table_JTAG
title	JTAG selection

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Signal	JTAGEN S2-4	M_JTAGEN S2-5	FMC_JTAG S2-6
CPLD MAX 10 (header J5)	OFFON	DNCXDNC	X
4x5 SoM CPLD (micro USB J10)	OFF	ON	OFF	OFF
4x5 SoC/FPGA (micro USB J10)	ONOFFON	OFF	OFF
FMC (micro USB J10)	ONOFF	DNCX	ON

Module control

The module control signals are connected to dip switches:

...

The push button signal is connected to the RESIN signal of the SoM (low active reset).

...

I²C and MUX

The SEL vector is used to select different I2C devices:

...

Scroll Title

anchor	Table_SC_I2C_MUX
title	SC I2C MUX ports

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

VHDL Port name	Direction	SC CPLD Pin	Connected to	Function	Notes
FMC_SCL	OUT	J8	J1, pin C31	I²C 2-wire serial bus	MUX in CPLD
FMC_SDA	INOUT	F9	J1, pin C30	I²C 2-wire serial bus	MUX in CPLD
FFA_MSEL	OUT	C9	J13, pin 4	Select attached FF Module	Pull low to use I²C
FFA_SCL	OUT	D6	J13, pin 8	I²C 2-wire serial bus	MUX in CPLD
FFA_SDA	INOUT	E6	J13, pin 7	I²C 2-wire serial bus	MUX in CPLD
FFB_MSEL	OUT	B10	J18, pin 4	Select attached FF Module	Pull low to use I²C
FFB_SCL	OUT	D8	J18, pin 8	I²C 2-wire serial bus	MUX in CPLD
FFB_SDA	INOUT	A9	J18, pin 7	I²C 2-wire serial bus	MUX in CPLD
A_01_P	OUT	K11	JB1, pin 37	SDA OUT	"three wire" I²C
A_06_N	IN	G12	JB1, pin 49	I2C GPIO MUX 0	I2C MUX also used for FireFlys MSEL
A_07	IN	L13	JB1, pin 34	I2C GPIO MUX 1	I2C MUX also used for FireFlys MSEL

PHY LEDs

As soon as the module M3_3VOUT is ready the The following signals are used to drive the PHY LEDs.

Scroll Title

anchor	Table_PHY_LEDs
title	Connection of PHY LEDs

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Signal	VHDLname	Function	Notes
CPLDA_IO05_1N	PHY_LED1	drive LED	Connected to JB1-8857
net_gnd	PHY_LED1R	select color	yellow
CPLDA_IO06_2P	PHY_LED2	drive LED	Connected to JB1-9251
net_gnd	PHY_LED2R	select color	green

...

Indication that PCIe Bus is up (power, clocks)

Scroll Title

anchor	Table_RGPIO
title	Signals handeld by RGPIO

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Signal	VHDLname	Function	Notes

SOC read

SoC write (

11

23)

PCIE_PERST

FF_RSTL	Reset configuration	Both FF are resetted simultanously when pulled LOW
SoC write (

17

22)

EN

SFPA_TX_

FMCEnable switched 3.3V FMC powerpulled down

DIS	SFP transmitter disable	HIGH disables transmitter
SoC write (

15

21)

PWR

SFPA_

EN_SignalEnable perepherie power 3V3_PERused for EN_PERSOC read (15)FMC_PRSNT_M2C_LIndicate if FMC installedLow when FMC present

RS0	SFP rate select RX	LOW for 1000BASE-SX, HIGH for 10GBASE-SR
SoC write (20)	SFPA_RS1	SFP rate select TX	LOW for 1000BASE-SX, HIGH for 10GBASE-SR
SoC write (19)	LED1	user LEDs
SoC write (18)	LED2	user LEDs
SoC write (17)	EN_FMC	Enable switched 3.3V FMC power	pulled down
SoC write (16)	FMC_PWR_set	Turn on FMC Power	used for EN_FMC_VADJ and FAN_FMC_EN

SOC read

SoC write (

14

15)

PG

PWR_

FMC

EN_

VADJIndicate FMC VADJ power is upSoC write (23)FF_RSTLReset configurationBoth FF are resetted simultanously when pulled LOW

Signal	Enable perepherie power 3V3_PER	used for EN_PER
SOC read (23

SOC read (21

)

FFA_

INTL

MPRS

Indicate

interrrupt

FF Module installed

LOW when

fault condition

Module present, pulled up

SOC read (

13

22)

FFA

FFB_MPRS	Indicate FF Module installed	LOW when Module present, pulled up
SOC read (

20

21)

FFB

FFA_INTL	Indicate interrrupt	LOW when fault condition, pulled up
SOC read (

22

20)

FFB_

MPRS

INTL

Indicate

FF Module installed

interrrupt

LOW when

Module present

fault condition, pulled up

SOC read (

17

19)

SFPA_

LOS

TX_FAULT

Indicates SFP

signal loss

laser fault

HIGH indicates

signal loss

fault
SOC read (18)	SFPA_M-DEF0	SFP modul absent	HIGH when module physically absent

SoC write

SOC read (

21

17)

SFPA_

RS0

LOS

SFP

rate select RXLOW for 1000BASE-SX, HIGH for 10GBASE-SRSoC write (20)SFPA_RS1SFP rate select TXLOW for 1000BASE-SX, HIGH for 10GBASE-SRSoC write (22)SFPA_TX_DISSFP transmitter disableHIGH disables transmitterSOC read (19)SFPA_TX_FAULTIndicates SFP laser faultHIGH indicates fault

signal loss	HIGH indicates signal loss
SOC read (16)	SDCD	SD card detect	Low when card inserted
SOC read (15)	FMC_PRSNT_M2C_L	Indicate if FMC installed	Low when FMC present
SOC read (14)	PG_FMC_VADJ	Indicate FMC VADJ power is up
SOC read (13)	OC_VSATA	Indicate SATA pin 7 overcurrent
SOC read (12)	USB_OC	Indicate USB overcurrent

SoC write (19)LED1user LEDsSoC write (18)LED2

Trenz Electronic Documentation

Versions Compared

Old Version 8

New Version Current

Key

Feature Summary

JTAG MUX

Module control

I²C and MUX

PHY LEDs

Appx. A: Change History and Legal Notices

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 8

New Version Current

Key

Feature Summary

JTAG MUX

Module control

I2C and MUX

PHY LEDs

Appx. A: Change History and Legal Notices

I²C and MUX