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HTML |
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<!-- tables have all same width (web max 1200px and pdf full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
width: 100% !important;
max-width: 1200px !important;
}
</style> |
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Important General Note:- If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
- Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
- Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
Figure template: Scroll Title |
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anchor | Figure_anchorname |
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title | Text |
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Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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- Table template:
- Layout macro can be use for landscape of large tables
Scroll Title |
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anchor | Table_tablename |
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title | Text |
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| Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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- The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
- type: Figure, Table
- main section:
- "OV" for Overview
- "SIP" for Signal Interfaces and Pins,
- "OBP" for On board Peripherals,
- "PWR" for Power and Power-On Sequence,
- "B2B" for Board to Board Connector,
- "TS" for Technical Specification
- "VCP" for Variants Currently in Production
- "RH" for Revision History
- name: custom, some fix names, see below
- Fix names:
- "Figure_OV_BD" for Block Diagram
- "Figure_OV_MC" for Main Components
- "Table_OV_IDS" for Initial Delivery State
- "Table_PWR_PC" for Power Consumption
- "Figure_PWR_PD" for Power Distribution
- "Figure_PWR_PS" for Power Sequence
- "Figure_PWR_PM" for Power Monitoring
- "Table_PWR_PR" for Power Rails
- "Table_PWR_BV" for Bank Voltages
- "Table_TS_AMR" for Absolute_Maximum_Ratings
- "Table_TS_ROC" for Recommended_Operating_Conditions
- "Figure_TS_PD" for Physical_Dimensions
- "Table_VCP_SO" for TE_Shop_Overview
- "Table_RH_HRH" for Hardware_Revision_History
- "Figure_RH_HRN" for Hardware_Revision_Number
- "Table_RH_DCH" for Document_Change_History
- Use Anchor in the document: add link macro and add "#<anchorname>
- Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>
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Note for Download Link of the Scroll ignore macro: |
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Notes :Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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- Pin headers (not soldered to the board, but included in the package as separate component)
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Scroll Title |
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anchor | Table_OV_RST |
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title | Reset process. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Signal | B2B | Signal State | Note |
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PROG_B | JM1-94 | Active Low | Clear FPGA configuration (falling edge) and initiate a new configuration sequenz (next rising edge). |
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Signals, Interfaces and Pins
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Scroll Title |
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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B2B Connector | Interface | Number of I/O | Notes |
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JM1
| User I/O | 52 Single ended, 27 Differential | - | MGT lanes | 4 Differential, 2 lanes |
| MGT reference clock input | 2 Single ended, 1 Differential |
| JTAG | 4 Single ended |
| SoM control signals | 2 Single ended | 'PROG_B', 'DONE' | JM2 | User I/O | 36 Single ended or 18 differential | - | SFP+ Interface control signals | 8 Single ended |
| QSPI interface | 6 Single ended |
| UART interface | 2 Single ended |
| User LEDs | 2 Single ended | Red, Green | SoM control signals | 1 Single ended | 'BOOTMODE' |
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Scroll Title |
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anchor | Table_SIP_PinHeader |
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title | General PL I/O to Pin headers information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin Header | Interface | Number of I/O | Notes |
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J17
| User I/O | 36 Single ended, 18 Differential | Module FPGA Bank 14 | SPI interface | 6 Single ended | - | Power | 4 Single ended | 3.3V, V_CFG | J20 | User I/O | 42 Single ended or 21 differential | Module FPGA Bank 34 | Power | 4 Single ended | 3.3V, V_CFG | User LEDs | 2 Single ended | Red, Green | SoM control signals | 1 Single ended | 'BOOTMODE' | J3 | JTAG | 4 Single ended |
| UART | 2 Single ended | B14_L25, B14_L0 | ADC | 2 Single ended |
| Clock | 2 Single ended, 1 Differential |
| Power | 4 Single ended | 3.3V, V_CFG | Control Signals | 2 Single ended | BOOTMODE, PROG_B | J4 | User I/O | 6 Single ended or 3 differential |
| Power | 2 Single ended | 3.3V, 3.3V_OUT |
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JTAG Interface Base
JTAG access to the mounted SoM is provided through B2B connector JM1 and JM2 and is also routed to the XMOD JTAG/UART header JX1.
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