Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Scroll Title
anchorFigure_OV_BD
titleTEF0003 block diagram


Scroll Ignore
draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision25
diagramNameTEF0003_OV_BD
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth641


Scroll Only


...

Scroll Title
anchorFigure_OV_MC
titleTExxxx TEF0003 main components


Scroll Ignore
draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision27
diagramNameTEF0003_OV_MC
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth641


Scroll Only


  1. Coaxial Connectors, J2-5
  2. SPI Flash, U9
  3. Xilinx Artix 7 FPGA, U1
  4. Lattice MachXO FPGA, U15
  5. Vita 57 Connector, J1
  6. EEPROM, U4
  7. I2C Switches, U2, U17-20
  8. Jumper, J7
  9. Serializer, U5-8
  10. Connector Header, J8
  11. Oscillator 25MHz, U11
  12. Programmable Clock Generator, U10
  13. Vita 57 Connector, J6
  14. ...
  15. ...
  16. ...

Initial Delivery State

Page properties
hiddentrue
idComments

Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

...

Include Page
IN:Legal Notices
IN:Legal Notices


draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision7
diagramNameTEF0003_OV_MC
simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth641