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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: | MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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| Scroll Title |
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| anchor | Table_OBP_MIOs |
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| title | MIOs pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Connected to | B2B | Notes |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | U11 Pin | Notes |
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| SPI-CS | CS |
| | SPI-CLK | CLK |
| | SPI-DQO | DI/IO0 |
| | SPI_DQ3 | HOLD/IO3 |
| | SPI-DQ2 | WP/IO2 |
| | SPI-DQ1 | DO/IO1 |
| | 1.8V | VCC |
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EEPROM
A Microchip 24LC128-I/LC serial EEPROM (U4) is provided for IPMI data. It is accessible via the LPC FMC connector J1 (SCL, SDA).
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Vita 57 Connector | Schematic | U4 Pin | Notes |
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| J1F-SCL | FMC_SCL | SCL |
| | J1F-SDA | FMC_SDA | SDA |
| | J1F-GA0 | GA0 | A0 |
| | J1F-GA1 | GA1 | A1 |
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Programmable Clock Generator
There is a Silicon Labs I2C programmable clock generator on-board (U10) to generate reference clocks for the module. Programming can be done using I2C via PIN header J8.
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| Scroll Title |
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| anchor | Table_OBP_PCLK |
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| title | Programmable Clock Generator Inputs and Outputs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Si5345A Pin
| Signal Name / Description
| Connected To | Direction | Note |
|---|
IN0 | Reference input clock. | U11 | Input | 25.00 MHz oscillator, SiT8008BI | | IN1 |
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A1
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| FMCT_GBTCLK0 | J6E | Input | Vita 57 Connector | | IN2 | FMCT_GBTCLK1 | J6E | Input | |Vita 57 Connector | | IN3 | FMCT_CLK0 | J6E | Input | Vita 57 Connector | XAXB | - | GND |
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| Input | 54.0000 MHz XTAL CX3225SB | | SCLK | PLL_SCL | J8, U20 | Input | EEPROM Programming | | SDA | PLL_SDA | J8, U20 | Input | EEPROM Programming | | OUT0 |
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| CLK8 | Not Conneted | Output |
| | OUT9 |
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Table 9: Programmable clock generator inputs and outputs.
Power and Power-On Sequence
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 7 |
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| diagramName | TEF0003_OV_MC |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramWidth | 641 |
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| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Si5345A Pin
| Signal Name / Description
| Connected To | Direction | Note |
|---|
IN0 | Reference input clock. | U11 | Input | 25.00 MHz oscillator, SiT8008BI | | IN1 | FMCT_GBTCLK0 | J6E | Input | Vita 57 Connector | | IN2 | FMCT_GBTCLK1 | J6E | Input | Vita 57 Connector | | IN3 | FMCT_CLK0 | J6E | Input | Vita 57 Connector | XAXB | - | GND | Input | 54.0000 MHz XTAL CX3225SB | | SCLK | PLL_SCL | J8, U20 | Input | EEPROM Programming | | SDA | PLL_SDA | J8, U20 | Input | EEPROM Programming | | OUT0 | GA_PCLK | U5/U1 | Output | FPGA bank 15 | | OUT1 | GB_PCLK | U6/U1 | Output | FPGA bank 15 | | OUT2 | GC_PCLK | U7/U1 | Output | FPGA bank 15 | | OUT3 | GD_PCLK | U8/U1 | Output | FPGA bank 15 | | OUT4 | CLK4_P | U1H | Output |
| | OUT5 | GBTCLK0 | J1E/J6E | Output |
| | OUT6 | GBTCLK1 | J1E/J6E | Output |
| | OUT7 | GBTCLK0 | J1E | Output |
| | OUT8 | CLK8 | Not Conneted | Output |
| | OUT9 | CLK9 | Not Conneted | Output | Not Used |
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