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- Coaxial Connectors, J2-5
- SPI Flash, U9
- Xilinx Artix 7 FPGA, U1
- Lattice MachXO FPGA, U15
- FMC Pcam Adapter, J1
- EEPROM, U4
- I2C Switches, U2, U17-20
- Jumper, J7
- Serializer, U5-8
- Connector Header, J8
- Oscillator 25MHz, U11
- Programmable Clock Generator, U10
- FMC Pcam Adapter, J6
Initial Delivery State
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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA | FPGA Bank | Connector Designator | I/O Signal Count | Voltage Level | Notes |
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| Artix 7, U1 | 16 | J1B | 68 Single Ended, 34 Differential | 1.8V |
| | 35 | J6B | 68 Single Ended, 34 Differential | 1.8V |
| | Lattice MachXO, U | 0 | J1F | 4 Single Ended | 3.3V |
| | 0 | J6F | 4 Single Ended | 3.3V |
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JTAG Interface
The Lattice MachXO (U15) is available to meet the requirement of a CPLD, JTAG access to the TEF0003 FMC MachXO is available through FMC Pcam Adapter J6. JTAG access to the Artix 7(U1) is available via MachXO, Bank 2.
| Scroll Title |
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| anchor | Table_SIP_JTGCPLDJTG |
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| title | CPLD JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | B2B Connector |
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| FMC_TMS | J6F-TCK | | FMC_TDI_TOP | J6F-J1-TDI | | FMC_TDO_TOP | J6F-TDO | | FMC_TCK | J6F-TCK | | JTAGEN | J7 |
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| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | Connected to | Note |
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| TMS | Lattice MachXO, U15 BankArtix 7 FPGA, U1 | Bank 2 Bank 0 |
| Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | | TDO | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | | TCK | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | | INIT | Artix 7 FPGA, U1 | Connected to 1.8 |
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MIO Pins
| Page properties |
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: | MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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